基于40nm的SAR ADC技术研究

发布时间：2018-06-04 07:32

本文选题：逐次逼近型ADC + 40nm工艺　；参考：《电子科技大学》2015年硕士论文

【摘要】：逐次逼近型SAR ADC(successive approximation A/D converter)具有结构简单、节省功耗的特点,因此随着工艺尺寸的减小,SAR ADC相对于其他ADC架构(例如pipelined ADC)逐渐显示出两大优势:(1)组成SAR ADC大部分电路为数字电路,在深亚微米及纳米级工艺下,数字电路可以达到更快的速度。(2)SAR ADC不需要一个高增益高带宽的运放来获取足够的线性度。一个高性能的运放不仅要占用较大的功耗,同时还要受到短沟道效应和电源电压的限制。这些SAR ADC的优势使其在低压低功耗应用领域逐渐受到设计者的青睐。本文基于40nm CMOS工艺,对逐次逼近型SAR ADC的系统架构和关键单元电路进行了深入的研究和分析,并设计了一个12位1MS/s的SAR ADC。首先,为了获得较优的系统架构,本文首先分析了DAC中影响系统性能的一些因素,主要包括电容失配,分段结构,寄生电容等。根据分析和推导结果,选取了全差分tri-level结构为DAC的基本架构。根据工艺厂商提供的单位电容值和失配的关系对DAC进行了MATLAB建模,选取了合适的单位电容值和分段结构,以保证在满足精度要求的前提下,尽量减小采样电容的值和功耗。然后着重研究了栅压自举开关、动态比较器和时序控制电路。由于本文的设计目标为12位的ADC,用传统的latch作比较器难以达到想要的精度。因为动态比较器与传统的静态比较器相比,不需要偏置电路,没有静态功耗,因此比较器选用了一个两级的动态比较器,第一级为动态预放大,第二级为latch。着重分析了影响动态比较器噪声的主要因素,并分析了减小动态比较器噪声的方法。最后,分析了深亚微米及纳米工艺下的STI效应和WEP效应,并介绍了在电路和版图中解决STI效应和WEP效应的方法。基于40nm CMOS工艺完成了各个关键单元电路以及整体SAR ADC版图的实现,并对整个12位1MS/s SAR ADC进行了后仿验证。后仿结果表明:在采样频率为1MHz,输入信号频率为456KHz的条件下,ADC的信号噪声失真比(SNDR)为73.77dB,无杂散动态范围(SFDR)为81.99dB,有效位数(ENOB)为11.96位。另外,所设计的ADC的功耗为0.67mW,版图面积为0.169mm2。
[Abstract]:Successive approximation SAR ADC(successive approximation A / D converters have the advantages of simple structure and low power consumption. Therefore, with the decrease of process size, SAR ADC is composed of digital circuits compared with other ADC architectures (such as pipelined ADC1). In deep submicron and nanoscale processes, the digital circuit can achieve a faster speed. The ADC does not require a high gain and high bandwidth operational amplifier to obtain sufficient linearity. A high performance operational amplifier not only takes up large power consumption, but also is limited by short channel effect and power supply voltage. The advantages of these SAR ADC make it more and more popular with designers in low-voltage and low-power applications. Based on 40nm CMOS process, the system architecture and key unit circuits of successive approximation SAR ADC are studied and analyzed in this paper, and a 12-bit 1MS/s SAR SAR ADC is designed. First of all, in order to obtain a better system architecture, this paper first analyzes some factors that affect the system performance in DAC, including capacitor mismatch, segmented structure, parasitic capacitance and so on. According to the results of analysis and derivation, the fully differential tri-level structure is selected as the basic structure of DAC. According to the relationship between unit capacitance value and mismatch provided by process manufacturer, the MATLAB model of DAC is built, and the appropriate unit capacitance value and segment structure are selected to ensure that the value and power consumption of the sample capacitance can be minimized under the premise of satisfying the precision requirement. Then, the gate voltage bootstrap switch, dynamic comparator and timing control circuit are studied. Because the design goal of this paper is 12-bit latch, it is difficult to achieve the desired precision by using traditional latch as comparator. Compared with the traditional static comparator, the dynamic comparator has no bias circuit and no static power consumption, so the comparator selects a two-stage dynamic comparator, the first stage is dynamic preamplifier, and the second stage is latch. The main factors influencing the noise of dynamic comparator are analyzed, and the methods to reduce the noise of dynamic comparator are analyzed. Finally, the STI effect and WEP effect in deep submicron and nanometer process are analyzed, and the methods to solve STI effect and WEP effect in circuit and layout are introduced. The realization of each key unit circuit and the whole SAR ADC layout based on 40nm CMOS process is completed, and the 12 bit 1MS/s SAR ADC is verified by post-simulation. The post-simulation results show that when the sampling frequency is 1 MHz and the input signal frequency is 456KHz, the signal noise distortion ratio (SNDR) is 73.77 dB, the non-spurious dynamic range is 81.99 dB, and the effective bit number is 11.96 bits. In addition, the power consumption of the designed ADC is 0.67 MW and the layout area is 0.169 mm ~ 2.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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