纳米CMOS组合电路单粒子诱导的软错误研究

发布时间：2018-06-04 18:50

本文选题：纳米CMOS组合电路 + 单粒子瞬态　；参考：《国防科学技术大学》2015年博士论文

【摘要】：我国航天科技的飞速发展,使得空间应用抗辐射集成电路的研究已经成为学术界和工业界的关注重点。随着工艺尺寸的缩减以及时钟频率的增加,组合电路中的软错误率已逐渐成为总的软错误率的主要来源。本文针对纳米尺度下的组合电路,对其软错误分析、测量及加固技术展开了深入的研究。主要取得如下几个方面的研究成果:(1)提出了处理重汇聚问题的SET混合时序传播算法,并首次获得了脉冲窄化效应对大规模组合电路软错误率影响的模拟数据。通过对粒子入射位置和脉冲窄化效应之间的关系进行建模,提出了考虑脉冲窄化效应的组合电路软错误率分析方法。模拟结果表明:脉冲窄化效应对软错误率的影响与具体的版图布局密切相关,对于不同的测试电路,脉冲窄化效应可以使其软错误率减少4-16%,当采用一种优化后的版图布局结构后,可以使其软错误率进一步减少。(2)从敏感区的角度研究了组合电路中的多SET现象,研究发现多SET敏感区的敏感性比单SET敏感区的敏感性低一个量级之上。提出了基于版图的简化多SET敏感区模型及面积计算方法,基于该模型分析了65 nm工艺下大规模组合电路中多SET的产生与传播概率。模拟结果表明:虽然多SET传播至末端锁存器的概率大于单个SET的传播概率,但是多SET的产生概率远低于单个多SET的产生概率。(3)提出了有效敏感区以及有效SET脉宽概念对纳米尺度下的敏感晶体管建模,并基于该概念对组合电路软错误率进行计算,研究发现:将漏区作为敏感区的方法会低估电路的软错误率一个量级之上。采用网格划分的方法对纳米尺度下晶体管的敏感区重新定义,在此基础上提出了有效敏感区及有效SET脉宽的概念,并通过重离子试验进行了验证。试验和模拟结果表明,有效敏感区概念更加接近真实的情况,将漏区作为敏感区的方法会低估组合电路的软错误率一个量级之上,给电路设计者带来过于乐观的结论。(4)提出了基于粒子入射位置的软错误率评估技术,该评估方法综合考虑了电荷共享效应、脉冲窄化效应、多SET、角度等因素。通过网格划分的特征化方法对粒子入射位置与SET脉冲宽度之间的关系进行建模,进而提出了基于粒子入射位置的组合电路软错误率评估技术,该技术考虑了纳米尺度下影响组合电路软错误率的诸多因素。模拟和重离子试验结果表明该技术能更加真实地反映组合电路的软错误率,可以更加细微地表征和统计单个入射粒子引起的电路级响应。(5)基于65 nm某商用体硅CMOS工艺,设计了三种新颖的组合电路软错误测量结构,并采用重离子试验获得了大规模组合电路中SET脉宽分布的试验数据。基于对称思想提出了三种组合电路软错误测量结构:反相器链的SET动态测量结构、分别测量PMOS和NMOS脉宽及电荷共享能力的结构、测量大规模组合电路软错误率的结构。在65 nm某商用体硅CMOS工艺下对这些测试电路进行了流片及功能测试,并采用重离子试验验证了测量大规模组合电路软错误率的测试结构,很好地弥补了国际上在试验测量方面的不足。(6)设计并实现了组合电路软错误的多层次加固技术,研究表明:在平均损失22.8%面积开销的情况下,该加固技术可以平均减少66.8%的软错误率。提出的多层次加固技术分别在工艺、单元、版图、电路等层次加固组合电路,采用统一的框架将各个层次的加固技术整合在一起,集成至商用的EDA工具中。模拟结果表明,该加固技术具有良好的加固性能,并且该技术可以根据具体的可靠性指标进行配置。
[Abstract]:With the rapid development of space science and technology in China, the research of space application anti radiation integrated circuits has become the focus of the academic and industrial circles. With the reduction of the technology size and the increase of the clock frequency, the soft error rate in the combinatorial circuit has gradually become the main source of the total soft error rate. An in-depth study of its soft error analysis, measurement and reinforcement technology is carried out. The main achievements are as follows: (1) a SET hybrid time series propagation algorithm is proposed to deal with the heavy convergence problem, and the simulation data of the impact of the pulse narrowing effect on the soft error rate of large scale composite circuits are obtained for the first time. The relationship between the incident position and the pulse narrowing effect is modeled, and the soft error rate analysis method of combinational circuit considering the pulse narrowing effect is proposed. The simulation results show that the influence of the pulse narrowing effect on the soft error rate is closely related to the specific layout layout. For different test circuits, the pulse narrowing effect can make it soft error. The rate of 4-16% is reduced. When the layout structure of an optimized layout is adopted, the soft error rate can be further reduced. (2) the multi SET phenomenon in the composite circuit is studied from the angle of the sensitive area. The sensitivity of the multi SET sensitive area is more than one order of magnitude lower than the sensitivity of the single SET sensitive area. A sense region model and an area calculation method are used to analyze the generation and propagation probability of multiple SET in a 65 nm process. The simulation results show that, although the probability of multiple SET propagation to the end latch is greater than the propagation probability of a single SET, the generation probability of multiple SET is far lower than the generation probability of a single multiple SET. (3) it is proposed. The effective sensitive area and the effective SET pulse width concept are used to model the sensitive transistors in nanoscale. Based on this concept, the soft error rate of the combinational circuit is calculated. It is found that the method of using the leaky region as a sensitive area will underestimate the soft error rate of the circuit. The method of grid partition is used to sensitist transistors in nanoscale. The sense region is redefined. On this basis, the concept of effective sensitive area and effective SET pulse width is proposed and verified by heavy ion test. The experimental and simulation results show that the concept of effective sensitive area is closer to the real situation. The method of using the leaky area as a sensitive area will underestimate the soft error rate of the combinatorial circuit on one order of magnitude. Road designers have brought too optimistic conclusions. (4) a soft error rate assessment technique based on particle incident position is proposed. The method takes into account the charge sharing effect, pulse narrowing effect, multi SET, angle and other factors. The relationship between the particle entry position and the SET pulse width is modeled by the characteristic method of grid division. Then a soft error rate assessment technique based on the particle incident position is proposed. The technology considers many factors that affect the soft error rate of the composite circuit under the nano scale. The simulation and heavy ion test results show that the technology can more truly reflect the soft error rate of the combinatorial circuit, and can be more subtle and statistical single. The circuit level response caused by incident particles. (5) based on a commercial silicon CMOS process in a commercial body of 65 nm, three novel soft error measurement structures are designed, and experimental data of the SET pulse width distribution in a large-scale combinational circuit are obtained by heavy ion test. Based on the symmetry idea, the soft error measurement structure of three combinational circuits is proposed. The SET dynamic measurement structure of the chain is used to measure the structure of the PMOS and NMOS pulse width and the charge sharing capability respectively. The structure of the soft error rate of the large scale composite circuit is measured. The flow sheet and function test of these testing circuits are tested under a commercial silicon CMOS technology of 65 nm, and the heavy ion test is used to verify the soft error rate of the large-scale combinational circuit. The test structure is good to make up for the shortage of test measurement in the world. (6) the multi-layer reinforcement technology is designed and realized. The research shows that the reinforcement technology can reduce the soft error rate by 66.8% on the average loss of 22.8% area, and the multi-layer reinforcement technology is in the process, respectively. Unit, layout, circuit and other layered composite circuits are integrated into a unified framework to integrate all layers of reinforcement technology into the commercial EDA tools. The simulation results show that the reinforcement technology has good strengthening performance and the technology can be configured according to the specific reliability index.
【学位授予单位】：国防科学技术大学
【学位级别】：博士
【学位授予年份】：2015
【分类号】：TN432

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