功耗可配置流水线模数转换器电路的研究与设计

发布时间：2018-06-07 02:10

本文选题：流水线 + 功耗可配置　；参考：《苏州大学》2015年硕士论文

【摘要】：以CMOS图像采集系统为代表的物联网技术近年来吸引了众多国内外研究者的目光,能够在不同数据更新率下保持较高的线性度与能量效率是图像采集设备的重要需求。解决这个需求的关键是使得该系统中的模数转换器实现功耗可配置,并且在不同速率下优化功耗。与此同时,芯片逐渐降低的电源电压给包括模数转换器在内的模拟电路设计带来了巨大的挑战。因此,低电源电压、高信号摆幅、高线性度的模数转换器逐渐成为了芯片设计的难点和重点。本课题设计的流水线型模数转换器主要在信号摆幅、线性度与功耗方面进行了优化,论文的主要创新点与改进措施在于:1)模数转换器使用了栅压自举开关,有效地提升了采样保持电路的线性度;在流水线的采样保持级与多功能增益级中采用全差分的两级运放,提高了信号的摆幅,并在两级运放的输出端使用开关电容共模负反馈电路,降低了该部分电路的功耗。2)系统结构上采用每级2.5位的流水线工作方式,改善由于电容失配引入的非线性;偏置电路中加入了由串行信号控制的电流调节电路,以此来优化由于运放工作点改变造成的线性度恶化。该流水线型模数转换器使用的工艺库为GSMC 0.18um RF CMOS工艺,版图总面积约为1.982mm。目前已经完成电路和版图设计,仿真结果表明:信噪比和线性度均达到10位以上。
[Abstract]:The Internet of things technology, represented by CMOS image acquisition system, has attracted the attention of many researchers at home and abroad in recent years. It is an important requirement for image acquisition equipment to maintain high linearity and energy efficiency under different data update rates. The key to solve this problem is to make the ADC in the system configurable and optimize the power consumption at different rates. At the same time, the decreasing supply voltage of the chip poses a great challenge to the design of analog circuits, including analog-to-digital converters. Therefore, low power supply voltage, high signal swing, high linearity A / D converter has gradually become the key point of chip design. The pipeline A / D converter designed in this paper has been optimized in the aspects of signal swing, linearity and power consumption. The main innovation and improvement measures of this paper are: 1) A / D converter uses gate voltage bootstrap switch. The linearity of the sampling and holding circuit is improved effectively, the full differential two stage operational amplifier is adopted in the sampling and holding stage and the multifunctional gain stage of pipeline, and the amplitude of the signal is increased. The switched capacitor common-mode negative feedback circuit is used in the output of the two-stage operational amplifier, which reduces the power consumption of this part of the circuit and adopts a 2.5 bit pipelined mode per stage to improve the nonlinearity caused by the capacitance mismatch. The current regulation circuit controlled by serial signal is added to the bias circuit to optimize the linearity deterioration caused by the change of operational amplifier operating point. The pipeline A / D converter uses a GSMC 0.18um RF CMOS process with a total layout area of about 1.982mm. The circuit and layout design have been completed, and the simulation results show that the signal-to-noise ratio (SNR) and linearity are above 10 bits.
【学位授予单位】：苏州大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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