基于动态误差校正的16位200MSPS电流舵DAC设计

发布时间：2018-06-11 14:30

本文选题：电流舵DAC + 16位　；参考：《电子科技大学》2017年硕士论文

【摘要】：世界工业的发展对具有高动态性能的高速、高精度DAC需求愈加旺盛。虽然国内半导体起步平台较低,技术积累较少,但是,随着科研人员不懈的攻坚克难,国内涌现了一大批优秀的高速、高精度DAC设计。顺应时代和需求之洪流,本文基于40nm CMOS工艺设计了一款16位200MSPS的电流舵DAC。本文首先对DAC的基本概念、基本架构做出了较为详细的解释,分别介绍并对比了不同架构DAC的优缺点和其具体应用环境。根据本文设计的指标和当前主流高速、高精度DAC的架构选择分段式电流舵作为本文DAC设计的基本架构。然后,本文对影响电流舵DAC动、静态性能的非理想因素进行了深入的研究并找出相对应的校正方案。在研究过程中,结合参考文献对部分非理想因素给予了充分的公式推导证明,对其校正算法的研究为本次校正算法的选择提供了较为充实的理论指导。在研究前述校正算法的同时提出了一种新的校正算法,该校正算法采用动态误差检测电路对电流源的动态误差进行检测,而后量化并对其电流源再匹配,从而实现了对16位200MSPS分段式电流舵DAC动态性能的提升。基于标准40nm CMOS工艺,结合该校正算法和16位200MSPS DAC的性能参数指标完成了电流舵DAC分段方案、电流源基本单元电路、高速低摆幅差分开关驱动电路、LVDS电路和动态误差检测电路等关键模块设计。最后,基于标准40nm CMOS工艺,完成了电流源基本单元电路、高速低摆幅差分开关驱动电路和LVDS电路等关键模块的版图设计,实现了对16位200MSPS DAC后仿验证。后仿验证结果表明:在输出信号频率为17.1875MHz,采样时钟频率为200MHz的条件下SFDR为93.062dB,整个DAC功耗为120mW,DAC核心版图面积为42mm。
[Abstract]:With the development of the world industry, the demand for high-speed and high-precision DAC with high dynamic performance is more and more strong. Although the domestic semiconductor starting platform is low and the technology accumulation is less, with the unremitting efforts of the researchers, a large number of excellent high speed and high precision DAC designs have emerged in our country. In this paper, a 16-bit 200MSPS current rudder DAC is designed based on 40nm CMOS process. In this paper, the basic concept and architecture of DAC are explained in detail, and the advantages and disadvantages of DAC with different architectures and its application environment are introduced and compared respectively. According to the index designed in this paper and the current mainstream high speed and high precision DAC architecture, the segmented current rudder is chosen as the basic architecture of the DAC design in this paper. Then, the non-ideal factors affecting the dynamic and static performance of the current-rudder DAC are studied and the corresponding correction schemes are found out. In the course of the study, some of the non-ideal factors are proved by formula derivation combined with references, and the research on the correction algorithm provides a more substantial theoretical guidance for the selection of the correction algorithm. At the same time, a new correction algorithm is proposed, which uses the dynamic error detection circuit to detect the dynamic error of the current source, and then quantifies and matches the current source. Thus, the dynamic performance of 16 bit 200MSPS segmented current rudder DAC is improved. Based on the standard 40nm CMOS process, combining with the correct algorithm and the performance parameter index of the 16-bit 200MSPS DAC, the current rudder DAC segmented scheme and the basic cell circuit of the current source are completed. The key modules such as LVDS circuit and dynamic error detection circuit are designed for high speed and low swing differential switch drive circuit. Finally, based on the standard 40nm CMOS technology, the layout design of the key modules, such as current source basic circuit, high-speed and low-swing differential switch driver circuit and LVDS circuit, is completed, and the post-simulation verification of 16-bit 200MSPS DAC is realized. The post-simulation results show that the SFDR is 93.062dBunder the output signal frequency of 17.1875MHz and the sampling clock frequency is 200MHz, and the power consumption of the whole DAC is 120mWN DAC core layout area of 42mm.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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