H.264基线档次解码器的设计与实现

发布时间：2018-06-12 08:43

本文选题：H.264 + 基线档次　；参考：《北京交通大学》2015年硕士论文

【摘要】：随着通信、电子科学技术和计算机技术的发展,人类进入了多媒体时代。H.264视频编解码协议在其中有着重要地位。而高速度、低功耗的H.264编解码芯片无疑是其中最重要的一环。本文采用SMIC180nm1P6M工艺,设计了一款H.264基线档次视频解码器。本文主要内容包括： 1、研究了视频压缩的基本理论以及H.264视频编解码协议,随后对H.264视频编解码标准的关键技术做了详细地研究与分析。 2、针对各关键技术的特点,提出了解码器工作的流水线和并行结构。随后设计了各关键技术的子模块,各子模块内部也使用了各自的流水线与并行结构。最后提出了验证方案,并对整个解码器进行了功能验证,功能验证的结果表明解码器能正确的解码H.264视频码流。 3、以smic180nm1P6M工艺,对解码器的RTL级Verilog HDL代码进行逻辑综合与布局布线,并提取参数、计算延迟,进行布线后仿真。布线后仿真的结果表明设计能够正确解码H.264视频码流。本文所设计的解码器的时钟频率为100MHz,可以实时解码每秒24帧的1920x1080分辨率视频编码码流。在1.98V的工作电压下,其功耗为151.6mW。最终实现芯片的等效门数为159K门以及总共20096字节的SRAM。芯片长宽为1670.24um×1662.88um。
[Abstract]:With the development of communication, electronic science and technology and computer technology, human has entered the multimedia era. H.264 video codec protocol plays an important role in it. The H.264 codec chip with high speed and low power consumption is undoubtedly the most important one. In this paper, a H.264 baseline video decoder is designed using SMIC180nm1P6M technology. The main contents of this paper are as follows: 1. The basic theory of video compression and H.264 video coding and decoding protocol are studied, and then the key technologies of H.264 video coding and decoding standard are studied and analyzed in detail. The pipelining and parallel architecture of the decoder are presented. Then the sub-modules of each key technology are designed, and each sub-module also uses its own pipeline and parallel structure. Finally, the verification scheme is proposed, and the function verification of the whole decoder is carried out. The result of function verification shows that the decoder can correctly decode the H.264 video stream. 3. The RTL level Verilog HDL code of the decoder is logically synthesized and wired in the smic180nm1P6M process. The parameters are extracted, the delay is calculated, and the post-wiring simulation is carried out. The simulation results show that the proposed decoder can decode the H.264 video stream correctly, and the clock frequency of the decoder is 100 MHz, which can decode the 1920x1080 video coding stream of 24 frames per second in real time. At 1.98 V, the power consumption is 151.6 MW. Finally, the equivalent gate number of the chip is 159 K gate and a total of 20096 bytes of SRAM. The length and width of the chip is 1670.24um 脳 1662.88 um.
【学位授予单位】：北京交通大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN764

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