10bit超低功耗SAR ADC设计

发布时间：2018-06-12 12:54

本文选题：逐次逼近型ADC + 低功耗　；参考：《国防科学技术大学》2015年硕士论文

【摘要】：逐次逼近型(SAR)ADC由于其结构简单、功耗低、易集成等优点,广泛应用于传感网络、生物芯片等低功耗领域。SAR ADC中的功耗主要来源于三部分:DAC电容阵列、数字控制逻辑以及比较器部分。本文以设计一款10bit200KSPS超低功耗SARADC为目标,从比较器、DAC电容阵列两方面提出降低功耗的优化方法。基于10bit超低功耗SAR ADC的应用需求,本文提出一种基于二进制加权电容DAC阵列的动态比较器失调校准技术,并基于65纳米CMOS工艺设计实现了一款低功耗低失调动态比较器。基于版图数据的模拟仿真结果表明,在1.2V的工作电压下,该校准技术可以将失调电压降低至0.25mV以内,功耗为0.33μW,功耗开销增大57%。虽然功耗略有增大,但这样的开销是值得的。此外,本文提出一种带错误补偿机制的两级电容开关时序方案,并基于65纳米CMOS工艺设计实现了两款SAR ADC,一种基于Switchback开关时序方案,一种基于两级电容开关时序方案,通过版图数据的模拟仿真结果对两款SAR ADC性能做比较,仿真结果显示SAR ADC的平均转换功耗降低35.6%,有效位数增大1.7%,说明带错误补偿机制的两级电容开关时序在保证性能(如有效位数)的基础上可以有效降低SAR ADC整体功耗。
[Abstract]:Because of its simple structure, low power consumption and easy integration, successive approximation ADC is widely used in sensor networks, biochips and other low-power fields. The power consumption in SAR ADC mainly comes from three parts: DAC capacitive array. Digital control logic and comparator section. Aiming at the design of a 10bit 200KSPS ultra-low power SARADC, this paper proposes an optimization method to reduce power consumption from two aspects of comparator DAC capacitor array. Based on the application requirement of 10bit ultra-low power 10bit, this paper presents a dynamic comparator offset calibration technique based on binary weighted capacitive DAC array, and implements a low power low offset dynamic comparator based on 65 nm CMOS process design. The simulation results based on layout data show that the proposed calibration technique can reduce the offset voltage to less than 0.25 MV, and the power consumption is 0.33 渭 W, and the power consumption is increased by 57%. Although the power consumption is slightly increased, the cost is worth it. In addition, a two-stage capacitor switch timing scheme with error compensation mechanism is proposed, and two SAR ADCs are implemented based on 65 nm CMOS process, one is based on switch timing scheme, the other is based on two-stage capacitor switch timing scheme. The performance of the two SAR ADC is compared by the simulation results of the layout data. The simulation results show that the average conversion power consumption of SAR ADC is reduced by 35.6and the effective bit number is increased by 1.7. the results show that the two-stage capacitor switch sequence with error compensation mechanism can effectively reduce the overall power consumption of SAR ADC on the basis of ensuring the performance (such as effective bit number).
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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