三维集成电路绑定前TSV缺陷检测方法研究
发布时间:2018-06-12 18:50
本文选题:三维集成电路 + 硅通孔 ; 参考:《北京化工大学》2016年硕士论文
【摘要】:随着集成电路技术的不断发展,基于硅通孔(TSV, Through Silicon Vias)技术集成的三维集成电路由于具备低延迟、高集成度、低功耗等优势而得到广泛的应用。通过TSV进行裸片间的堆叠绑定,能够显著减少芯片中长互连的延迟,从而提升芯片的性能。然而,由于TSV制造工艺的影响,TSV在制造和绑定过程中易于导致漏电等缺陷问题。如果通过使用包含缺陷的TSV对裸片进行堆叠集成,易于导致最终的三维集成电路产品失效,从而严重影响三维集成电路的良率。因此,非常有必要对TSV进行绑定前的缺陷检测,从而避免使用具有缺陷TSV的裸片进行三维集成电路堆叠集成,达到提高三集成电路产品的良率并以此降低制造成本的目的。在本篇论文中,我们设计了一种TSV漏电缺陷的检测结构,其能够在三维集成电路绑定前对TSV进行有效的漏电缺陷检测。这种方法基于TSV的电容和电阻特性,将TSV的漏电电流转化为漏电电压的形式进行检测。在检测过程中,首先对TSV进行充电,利用可编程型检测信号生成器将TSV在预期的时间下控制为高阻状态。然后通过对TSV在高阻漏电后的电压值进行采样,并依据采样结果确定TSV是否存在漏电缺陷。通过仿真实验的结果表明,本文设计的检测结构功能可行,且具有较大的TSV漏电缺陷检测范围,且制造成本相对较低,功耗小。
[Abstract]:With the continuous development of integrated circuit technology, 3D integrated circuits based on silicon through hole TSVand through Silicon Vias technology have been widely used because of their advantages of low delay, high integration, low power consumption and so on. The stacking binding between bare chips by TSV can significantly reduce the delay of long interconnect in the chip and improve the performance of the chip. However, due to the influence of TSV manufacturing process, TSV is prone to lead to defects such as leakage during fabrication and binding. If the bare chip is stacked and integrated with TSV containing defects, it is easy to lead to the final failure of 3D integrated circuit products, thus seriously affecting the yield of 3D integrated circuit. Therefore, it is necessary to detect the defects of TSV before binding, so as to avoid the use of defective TSV bare chips for 3D integrated circuit stacking and integration, so as to improve the yield of three integrated circuit products and reduce the manufacturing cost. In this paper, we design a TSV leakage defect detection structure, which can detect TSV leakage defect effectively before 3D IC binding. Based on the capacitance and resistance characteristics of TSV, the leakage current of TSV is converted to the form of leakage voltage. In the detection process, the TSV is first charged, and the TSV is controlled to a high resistance state in the expected time by using a programmable detection signal generator. Then the voltage value of TSV after high resistance leakage is sampled, and it is determined whether TSV has leakage defect or not. The simulation results show that the structure designed in this paper is feasible and has a large detection range of TSV leakage defects, and the manufacturing cost is relatively low and the power consumption is low.
【学位授予单位】:北京化工大学
【学位级别】:硕士
【学位授予年份】:2016
【分类号】:TN407
【参考文献】
相关期刊论文 前1条
1 余乐;杨海钢;谢元禄;张甲;张春红;韦援丰;;三维集成电路中硅通孔缺陷建模及自测试/修复方法研究[J];电子与信息学报;2012年09期
,本文编号:2010712
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