一种低功耗双重测试数据压缩方案

发布时间：2018-06-12 20:46

本文选题：测试向量相容 + 低功耗测试　；参考：《电子学报》2017年06期

【摘要】：随着集成电路制造工艺的发展,VLSI(Very Large Scale Integrated)电路测试面临着测试数据量大和测试功耗过高的问题.对此,本文提出一种基于多级压缩的低功耗测试数据压缩方案.该方案先利用输入精简技术对原测试集进行预处理,以减少测试集中的确定位数量,之后再进行第一级压缩,即对测试向量按多扫描划分为子向量并进行相容压缩,压缩后的测试向量可用更短的码字表示;接着再对测试数据进行低功耗填充,先进行捕获功耗填充,使其达到安全阈值以内,然后再对剩余的无关位进行移位功耗填充;最后对填充后的测试数据进行第二级压缩,即改进游程编码压缩.对ISCAS89基准电路的实验结果表明,本文方案能取得比golomb码、FDR码、EFDR码、9C码、BM码等更高的压缩率,同时还能协同优化测试时的捕获功耗和移位功耗.
[Abstract]:With the development of integrated circuit manufacturing technology, VLSI-Very large scale integrated circuit testing is faced with the problems of large amount of test data and high power consumption. In this paper, a low power test data compression scheme based on multistage compression is proposed. In this scheme, the original test set is preprocessed by input reduction technique to reduce the number of test sets, and then the first stage compression is carried out, that is, the test vectors are divided into subvectors according to multiple scans and compatible compression is carried out. The compressed test vector can be represented by a shorter codeword, then the test data is filled with low power consumption, and the power consumption is first captured to reach the safe threshold, and then the remaining independent bits are filled with shift power consumption. Finally, the test data after filling is compressed by the second stage, that is, the improved run coding compression. The experimental results of the ISCAS89 reference circuit show that the proposed scheme can achieve a higher compression ratio than the golomb code / EFDR code / 9C code / BM code. At the same time, it can also cooperate to optimize the acquisition power consumption and the shift power consumption of the test.
【作者单位】：合肥工业大学计算机与信息学院;合肥工业大学情感计算与先进智能机器安徽省重点实验室;合肥工业大学电子科学与应用物理学院;德岛大学;
【基金】：国家自然科学基金(No.61204046,No.61474035,No.61306049);国家自然科学基金重点项目(No.61432004) 高等学校博士学科点专项科研新教师基金(No.2013JYXJ0650)
【分类号】：TN407

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