基于March算法的SRAM内建自测试设计与验证

发布时间：2018-06-15 23:16

本文选题：SRAM + 存储器内建自测试　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：深亚微米工艺技术的不断发展和人们对数据存储需求的不断提高,共同促进了存储器技术的飞速发展,存储器的重要性也越发显现。这主要表现为嵌入式存储器在整个SoC系统中的应用越来越多,所占比重越来越大。然而,由于嵌入式存储器往往深嵌在芯片内部,与其直接相连的I/O端口很少,很难实现对嵌入式存储器的直接控制和观察,大大增加了测试难度;另一方面,随着工艺尺寸的缩小,芯片上存储器密度的增加和存储器本身的复杂度不断提高,使得存储器不断出现新的故障类型,测试数据越来越庞大,极大的增加了测试成本,原始的测试方法已经难以应对这些新的挑战。本文讨论的存储器内建自测试技术恰是专门针对于嵌入式存储器的一种行之有效的测试技术。存储器内建自测试技术主要是通过在待测存储器外围加入BIST电路,自动实现测试数据的内部生成、向量施加和结果分析,从而达到在电路内部检测存储器故障的目的。存储器内建自测试技术凭借其操作简单、覆盖率高、成本低等优点成为目前存储器测试的主流技术。本文围绕SoC中的嵌入式存储器内建自测试技术主要完成了以下几项工作:(1)提出了改进的March LR测试算法。通过从测试时间、故障覆盖率和故障覆盖范围三个方面对比分析各种存储器测试算法的优劣,得到最优测试算法March LR算法。针对March算法无法覆盖地址内字间故障的缺陷,结合故障模型的相关理论知识,提出了改进的March LR测试算法。改进后的算法在保持对原有故障的覆盖上,增加了对地址内位间故障的覆盖,提高了故障覆盖范围和故障覆盖率。(2)设计了以SRAM为待测存储器,以改进的March LR算法为测试算法的存储器内建自测试电路。本文对测试电路的各个组成部分进行了模块化设计,其中详细设计了作为测试算法硬件实现的内建自测试控制器,最后编写了测试算法自定义文件,应用相关工具进行了代码的生成和插入。(3)设计了多存储器的存储器内建自测试电路。在单存储器内建自测电路的基础上,提出了多存储器情况下的测试电路设计方法,集中解决了测试输入输出占用引脚信号过多的问题。(4)实现了单存储器内建自测试电路的仿真与验证。对设计出的单存储器自建自测试电路进行了仿真验证,并对照波形图详细分析了测试算法的执行过程。仿真结果表明本文设计的测试算法和MBIST电路可以检测更多的存储器故障,达到了预期效果。
[Abstract]:With the development of deep submicron technology and the increasing demand for data storage, the rapid development of memory technology is promoted, and the importance of memory becomes more and more obvious. This mainly shows that embedded memory is applied more and more in the whole SoC system, which accounts for more and more. However, because embedded memory is often embedded in the chip and there are few I / O ports directly connected with it, it is difficult to realize the direct control and observation of embedded memory, which greatly increases the difficulty of testing. With the decrease of process size, the increase of memory density on chip and the increasing complexity of memory itself, new fault types appear continuously in memory, and the test data become larger and larger, which greatly increases the cost of testing. The original test method has been difficult to meet these new challenges. The memory built-in self-test technology discussed in this paper is an effective test technique for embedded memory. The technology of memory built-in self-test is mainly by adding BIST circuit to the periphery of the memory to be tested, automatically realizing the internal generation of test data, vector application and result analysis, so as to detect the memory failure inside the circuit. Memory built-in self-test technology has become the mainstream memory testing technology because of its simple operation, high coverage and low cost. In this paper, an improved March LR testing algorithm is proposed, which focuses on the embedded memory built-in self-test technology in SoC. By comparing and analyzing the advantages and disadvantages of various memory test algorithms from three aspects of test time, fault coverage and fault coverage, the optimal test algorithm March LR is obtained. Aiming at the defect that March algorithm can not cover inter-word faults within addresses, an improved March LR testing algorithm is proposed based on the relevant theoretical knowledge of fault model. In order to keep the coverage of the original faults, the improved algorithm increases the coverage of the faults between the addresses, and improves the fault coverage and the fault coverage. (2) the SRAM is designed as the memory to be tested. The improved March LR algorithm is used as the memory of the test algorithm to build self test circuit. In this paper, the modular design of each component of the test circuit is carried out, in which the built-in self-test controller is designed as the hardware implementation of the test algorithm in detail. Finally, the test algorithm custom file is written. The code generation and insertion with related tools are used to design the memory built-in self-test circuit with multi-memory. On the basis of self-test circuit built in single memory, the design method of test circuit with multi-memory is proposed. The problem of too many input / output pin signals is solved in this paper. The simulation and verification of a single memory built-in self-test circuit is realized. The self-built self-test circuit with single memory is simulated and verified, and the execution process of the test algorithm is analyzed in detail compared with the waveform diagram. The simulation results show that the test algorithm and MBIST circuit designed in this paper can detect more memory faults and achieve the desired results.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN407

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