干法刻蚀辅助型GaN MOSFET的器件工艺及电学特性研究

发布时间：2018-06-18 13:13

本文选题：氮化镓 + MOSFET　；参考：《大连理工大学》2015年博士论文

【摘要】：GaN半导体具有禁带宽度大、临界击穿电场高、载流子饱和漂移速度高等优异特性,是制造大功率、高频、高温等器件的理想材料。与AlGaN/GaN HEMT相比,GaN MOSFET具有栅漏电流小、栅电压工作范围大、不需额外栅极驱动电路及容易制作成增强型器件等优点,故而广受关注。然而受限于实际p-GaN晶体质量较差、本征氧化层禁带宽度较窄等问题,GaN MOSFET较难通过传统的Si MOSFET工艺实现。采用AlGaN/GaN异质结结构虽能实现GaN MOSFET,但其栅区沟槽干法刻蚀的损伤会使器件界面态密度增大、阈值电压负漂,最终导致器件性能下降。此外,干法刻蚀工艺还会使器件沟道尺寸发生变化,导致器件迁移率评价出现较大误差。因此,如何实现GaN MOSFET、怎样去除沟槽干法刻蚀损伤、如何正确评价器件的沟道迁移率等都是需要研究的问题。针对以上问题,本文对AlGaN/GaN异质结上GaN MOSFET进行了器件和工艺设计,对其中关键的栅区沟槽干法刻蚀等工艺进行了优化,提出了改进的沟道迁移率评价新方法。此外利用干法刻蚀损伤机理,开发了三种新型低温及非合金GaN、AlGaN上的欧姆接触工艺,并通过这些工艺实现了先栅结构GaN MOSFET、自对准结构GaN MOSFET及AlGaN/GaN HEMT等新型器件。这些器件中都利用了干法刻蚀工艺,形成沟槽栅或低温欧姆接触。干法刻蚀工艺贯穿了本文的整个研究,这也是论文题目的由来。论文主要研究内容及结果如下：(1) AlGaN/GaN异质结结构的GaN MOSFET的版图工艺设计及沟槽干法刻蚀的研究。采用L-Edit设计了AlGaN/GaN异质结上的GaN MOSFET版图,并对其进行了工艺实现。同时对GaN MOSFET中关键的沟槽干法刻蚀工艺进行了预备实验,通过原子力显微镜(AFM)对不同干法刻蚀阻挡层、刻蚀气体流量、反应室压强等条件下刻蚀出的GaN样品进行了扫描,研究了其沟槽形貌、表面粗糙度、刻蚀速率等情况。实验结果表明,采用光刻胶作刻蚀阻挡层时,阻挡层侧墙对刻蚀离子的反射作用,会导致沟槽出现侧墙处过度刻蚀现象,采用Si02作阻挡层则不会出现此现象。此外采用较高刻蚀气体流量时,刻蚀面会出现颗粒状突起使其表面变粗糙。当反应室的压强较大时,干法刻蚀过程中的沉积效应将会增强,刻蚀速率显著降低且有副产物沉积于刻蚀面。最终实验初步确定了沟槽干法刻蚀的优选工艺条件,即采用Si02作为干法刻蚀阻挡层、在较小的气体流量(3 sccm)与反应室压强(0.25 Pa)条件下,干法刻蚀后的样品的沟槽形貌较好,表面平整粗糙度较小且副产物在表面沉积较少。(2) GaN MOSFET沟道迁移率评价方法的研究与改进。在条形的GaN MOSFET器件中发现了因为不良场隔离现象导致的平行沟道现象,它会使得器件的沟道迁移率被高估。在对沟道长度较小的器件进行评价时由于沟槽过刻的现象会导致制作出来的器件栅长大于版图的设计栅长,使得器件的沟道迁移率值被低估。本文通过实验证实并分析了以上现象,提出了四种在沟道尺寸有变化情况下正确提取GaN MOSFET迁移率的改进方法。此外本章也就GaN MOS系统的界面态密度评价方法做了简单说明,针对其中一些问题提出了有效的改进措施。实验结果显示这四种方法不仅可以准确提取出器件沟道迁移率值,也可以估算因为沟槽过度刻蚀所带来的沟道长度的变化量。用这些改进方法所得到的沟道迁移率值和长沟道环形器件中迁移率标准值一致,表明这些方法合理有效。(3) AlGaN/GaN异质结结构GaN MOSFET的工艺依赖性研究。实验中具体研究了沟槽干法刻蚀阻挡层、刻蚀气体种类及步骤、刻蚀Bias功率、栅氧化层种类及其厚度等对GaN MOSFET器件性能的影响,结合XPS等手段对导致器件阈值电压负漂的干法刻蚀损伤进行了分析评价,并通过电学测试的方法定量研究了MOS界面的等效电荷密度。针对这些问题开发了氮等离子体(N+)及氨水处理(NH4OH)方法,有效修复和去除了沟槽干法刻蚀损伤。实验表明采用Si02作干法刻蚀阻挡层、SiCl4做刻蚀气体、较小的干法刻蚀Bias功率、硅烷基PECVD制作的栅Si02层是比较优化的工艺。此外,通过XPS及电学测试发现在MOS界面处存在1012 q/cm2数量级的正电荷,它们很可能是由沟槽干法刻蚀过程中的干法刻蚀损伤引起。通过NH4OH处理,可以有效的去除干法刻蚀损伤,得到沟道迁移率为148.12 cm2/Vs的增强型GaN MOSFET。相应的MOS二极管中提取到的界面态密度在EC-ET为0.2到0.6 eV的可测范围内约为3×1011 cm-2eV-1，较干法刻蚀后的界面态密度值显著下降。(4)三种新型低温及非合金GaN、AlGaN上欧姆接触新工艺的开发与其在新型先栅结构GaN MOSFET、自对准结构GaN MOSFET及AlGaN/GaN HEMT中的应用研究。首先利用干法刻蚀损伤辅助工艺开发了一系列GaN、AlGaN上非合金和低温欧姆接触工艺,并对其中机理进行了分析解释,对制作出的欧姆接触进行了评价。结合比较独特的双层胶光刻工艺,开发制作了新型先栅结构GaN MOSFET、自对准结构的GaN MOSFET和AlGaN/GaN HEMT,并对其进行了电学评价,对一些不理想的因素进行了分析,提出了相应的改进措施。结果表明采用非合金欧姆接触工艺的先栅结构GaN MOSFET性能优异,其沟道迁移率达到了163.8 cm2/Vs。采用低温欧姆工艺的自对准结构的GaN MOSFET和AlGaN/GaN HEMT可以工作,且制作工艺可以进一步优化来使器件的性能更加优异。
[Abstract]:GaN semiconductor has high band gap width, high critical breakdown electric field and high carrier saturation drift speed, which is the ideal material for high power, high frequency and high temperature devices. Compared with AlGaN/GaN HEMT, GaN MOSFET has small gate leakage current and large grid voltage working range, without additional gate drive circuit and easy to be made into enhanced type Because of the poor quality of the p-GaN crystal and the narrow band gap of the intrinsic oxidation layer, the GaN MOSFET is more difficult to be realized by the traditional Si MOSFET process. The AlGaN/GaN heterostructure can realize GaN MOSFET, but the damage of the dry etching of the gate groove will increase the density of the interface state. The negative drift of threshold voltage leads to the decrease of device performance. In addition, the dry etching process will also change the channel size of the device, which leads to the large error in the evaluation of the mobility of the device. Therefore, how to realize the GaN MOSFET, how to remove the dry etching damage of the groove and how to correctly evaluate the channel mobility of the device are all needed to be studied. In view of the above problems, the design of GaN MOSFET on AlGaN/GaN heterojunction is designed, and the key technology of dry etching of the gate groove is optimized, and a new method of improving the channel migration rate is proposed. In addition, three new types of low temperature and unalloyed GaN, AlGaN are developed by using the mechanism of the dry etching damage. The ohmic contact process has been carried out. Through these processes, the first gate structure GaN MOSFET, the self aligned GaN MOSFET and AlGaN/GaN HEMT devices are used. These devices all use the dry etching process to form the groove gate or low temperature ohmic contact. The dry etching process runs through the whole study of this article, which is the origin of the thesis. The main contents and results of this thesis are as follows: (1) the layout process design of GaN MOSFET for AlGaN/GaN heterostructure and the study of trench dry etching. The GaN MOSFET layout of AlGaN/GaN heterojunction was designed with L-Edit, and the process was realized. The key groove dry etching process in GaN MOSFET was prepared. The experiment was conducted by atomic force microscopy (AFM) to scan the GaN samples etched by different dry etching barrier layers, etching gas flow and reaction chamber pressure, and the groove morphology, surface roughness and etching rate were studied. The reflection effect will lead to excessive etching in the side wall of the groove, and the phenomenon will not appear by using Si02 as the barrier layer. In addition, when the high etching gas flow is used, the etching surface will appear granular protuberance and make the surface roughness. When the pressure of the reaction chamber is larger, the deposition effect in the dry etching process will be enhanced and the etching rate will be increased. In the final experiment, the optimum technological conditions for the dry etching of the grooves were determined, that is, the Si02 was used as the dry etching barrier. Under the condition of the smaller gas flow (3 SCCM) and the pressure of the reaction chamber (0.25 Pa), the groove shape of the sample after the dry etching was better and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was smaller and the surface roughness was less. The side products are less deposited on the surface. (2) the study and improvement of the GaN MOSFET channel mobility evaluation method. The parallel channel phenomenon caused by the bad field isolation is found in the bar shaped GaN MOSFET device, which makes the channel mobility of the device overestimated. The phenomenon will lead to the design of the gate length larger than the layout, which makes the channel mobility of the device underestimated. In this paper, the above phenomena are confirmed and analyzed by experiments. Four kinds of methods to correct the transfer rate of GaN MOSFET under the change of channel size are proposed. In addition, this chapter is also on the bounds of the GaN MOS system. The surface density evaluation method is simply explained, and some effective improvement measures are put forward for some of the problems. The experimental results show that these four methods can not only accurately extract the mobility of the channel channel, but also estimate the variation of channel length caused by the excessive groove etching. The mobility values are in accordance with the standard mobility standard values in the long channel ring devices, indicating that these methods are reasonable and effective. (3) the process dependence of the AlGaN/GaN heterostructure GaN MOSFET. In the experiment, the dry etching barrier layer, the types and steps of the etching gas, the etching Bias power, the type and thickness of the gate oxide layer and the thickness of GaN MOSF are studied in the experiment. The effects of the performance of ET devices are analyzed by means of XPS and other means. The equivalent charge density of the MOS interface is quantitatively studied by electrical testing. The nitrogen plasma (N+) and ammonia water treatment (NH4OH) method is developed for these problems, and the groove is effectively repaired and removed. Dry etching damage. The experiment shows that Si02 is used as a dry etching barrier layer, SiCl4 is etching gas, small dry etching of Bias power, and the grid Si02 layer produced by silane PECVD is a relatively optimized process. In addition, there is a 1012 q/cm2 order of positive charge at the MOS interface by XPS and electrical testing. They are likely to be trench dry. Dry etching damage in the process of etching can be caused by NH4OH treatment, and the dry etching damage can be effectively removed. The interface state density extracted from the MOS diode of the enhanced GaN MOSFET. with a channel mobility of 148.12 cm2/Vs is about 3 x 1011 cm-2eV-1 in the range of 0.2 to 0.6 eV, compared with the dry etching. The density of the interface states decreased significantly. (4) the development of three new cryogenic and unalloyed GaN, AlGaN ohm contact new processes and its application in the new gate structure GaN MOSFET, the self aligned GaN MOSFET and AlGaN/GaN HEMT. First, a series of GaN, non alloy and low temperature on AlGaN were developed by the dry etching damage auxiliary technology. The ohm contact process was analyzed and the mechanism was analyzed. The ohm contact was evaluated. Combined with a unique double layer photolithography process, a new gate structure GaN MOSFET, GaN MOSFET and AlGaN/GaN HEMT with self aligned structure were developed and the electrical evaluation was carried out, and some undesirable factors were carried out. The results show that the first gate structure of the non alloy ohm contact process GaN MOSFET has excellent performance, the channel migration rate is 163.8 cm2/Vs., and the self aligned GaN MOSFET and AlGaN/GaN HEMT with low temperature ohm process can work, and the fabrication process can be further optimized to make the device. The performance is better.
【学位授予单位】：大连理工大学
【学位级别】：博士
【学位授予年份】：2015
【分类号】：TN386

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