基于FPGA的无相位截断误差DDS研究

发布时间：2018-06-19 20:00

本文选题：无相位截断 + 直接数字合成器　；参考：《电子科技大学》2015年硕士论文

【摘要】：近年来,应用于雷达、通信等领域的电子设备对信号频率稳定性和精确性的要求日益趋于严格,直接数字合成技术已经成为国内外学者研究重点和热点。随着现代科技与制造工艺的飞速提高,直接数字频率合成技术的体系结构和性能指标都得到了不同程度的提升与优化,但此技术产生的信号误差是不能忽略的。本文针对直接数字频率合成技术DDS的结构进行了分析,重点研究了DDS所产生信号的杂散,并从工作原理和理论推导等方面分析了DDS产生一系列杂散的原因。对传统DDS的相位截断误差、幅度量化误差、DAC非线性的理想特性转化误差等方面分析。分析了常见的无相位截断误差DDFS与传统的DDFS设计中的不同之处。提出一种有别于传统方法的无相位截断误差DDFS方案,通过Matlab对系统仿真分析并结合FPGA来验证其合理性和可行性。本文研究的主要工作内容包括:(1)对传统DDFS的结构进行阐述和理论分析,从数学角度对DDFS产生杂散的主要原因进行分析。并对PLL的结构和锁相原理进行了分析。此后,对当前所提出消除杂散的方法,如抖动注入法、ROM表压缩及延时叠加法等方法进行研究与分析。(2)分析了一种常见的消除相位截断误差的方法,提出了一种新的无相位截断DDFS结构,在不截断低段相位字的情况下减小ROM表的存储深度,并对由高段相位字所查找的幅度进行修正,消除相位截断所带来的误差。本文用Matlab与FPGA对此方法进行验证,并进行功能仿真,相较于传统方法,此结构能够更有效的消除相位截断误差。(3)分析DDFS+PLL各种方案,利用DDFS+PLL方案把无相位截断误差的DDFS输出信号作为锁相环电路的鉴相输入、负反馈端输入和环外混频、环内混频,并将无相位截断误差DDFS+PLL进行Matlab仿真,验证方案的可行性。
[Abstract]:In recent years, the requirements of signal frequency stability and accuracy for electronic devices used in radar, communication and other fields have become increasingly strict, and direct digital synthesis technology has become the focus and hotspot of scholars at home and abroad. With the rapid improvement of modern science and technology and manufacturing technology, the architecture and performance index of direct digital frequency synthesis technology have been improved and optimized to varying degrees, but the signal error caused by this technology can not be ignored. In this paper, the structure of direct digital frequency synthesizer (DDS) is analyzed, and the spurious signal generated by DDS is studied, and the causes of DDS are analyzed from the aspects of working principle and theoretical derivation. The phase truncation error and amplitude quantization error of traditional DDS are analyzed in this paper. The differences between DDFs without phase truncation error and traditional DDFS design are analyzed. A phase truncation error free DDFS scheme is proposed, which is different from the traditional method. The rationality and feasibility of DDFS are verified by Matlab simulation and FPGA. The main work of this paper includes: 1) expatiating and analyzing the structure of traditional DDFS, and analyzing the main reasons of the stray from the point of view of mathematics. The structure and phase locking principle of PLL are analyzed. After that, a common method of eliminating phase truncation error is studied and analyzed, such as jitter injection method, ROM table compression method and delay superposition method. In this paper, a new phase-free truncation DDFS structure is proposed, which reduces the storage depth of ROM table without truncating low-segment phase words, and corrects the amplitude searched by high-segment phase words to eliminate the errors caused by phase truncation. In this paper, Matlab and FPGA are used to verify this method, and the function simulation is carried out. Compared with the traditional method, this structure can eliminate the phase truncation error more effectively and analyze various schemes of DDFS PLL. The DDFS output signal with no phase truncation error is used as the phase discrimination input, the negative feedback end input and the external mixing, and the intra-loop mixing in DDFS PLL scheme. The simulation of DDFS PLL without phase truncation error is carried out in Matlab to verify the feasibility of the scheme.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN741

【共引文献】