基于MET的高压VDMOS器件模型研究

发布时间：2018-06-21 14:43

本文选题：SPICE模型 + 高压VDMOS模型　；参考：《杭州电子科技大学》2015年硕士论文

【摘要】：功率VDMOS(Vertical Conduction Double-Diffused Metal Oxide Semicondu ctor)(垂直双扩散场效应晶体管)器件是功率电子的主流产品之一。凭借其输入阻抗高、安全工作区宽、开关速度快和热稳定性好等很多特点,VDMOS广泛地应用于开关电源、电机驱动、节能灯和汽车电子部件等各种领域。我国在VDM OS器件研究方面已经取得了不少进展,但是还不够成熟,而且我国很多VDMO S产品需要进口,于是,对功率VDMOS器件的特性探究及其模型建立和模型优化存在着非常重要的意义。论文选取士兰微电子近期推出了新一代高压MOSFET产品——S-RinTM系列高压VDMOS,应用于AC-DC功率电源,DC-DC转换器以及PWM马达驱动等领域。本文简要介绍了VDMOS应用和发展前景以及模型研究的意义,概述了模型相关理论,包括SPICE模型及其发展,还有MET模型的特点和主要考虑的器件物理机制,接着介绍器件测试系统和模型提取软件及较详细全面的模型提取步骤,然后介绍功率VDMOS的结构发展以及分析了其直流特性、热温度特性和动态电容特性,最后对VDMOS进行直流测试和动态电容测试,包括输出特性曲线、转移特性曲线(I-V曲线)以及动态电容曲线(C-V曲线),选择模型提取软件对VDMOS建模。过程中发现初始MET模型由于主要是面向横向结构MOSFET器件,所以无法很好地对VDMOS器件进行表征。由此,在MET模型的基础上,在VDMOS的漏极添加一个受栅极电压跟漏极电压控制的电阻,很好地拟合VDMOS测试数据,提高模型精度,同时论文还在MET模型的VA(Verilog-A)模型文件中进行一些改动,在Verilog-A代码中修改原始方程,添加个别主要用于拟合线性区和饱和区的参数,从而使得优化后的MET模型仿真曲线与VDMOS实际IV特性相符。对于CV曲线拟合的解决办法,论文主要是对实测数据进行一个分段函数的近似,然后把分段函数用子电路的形式表达出来,最后通过Cadence仿真得到的CV曲线拟合度较高,典型器件Id-Vg曲线误差Err:MAX=100%|RMS=16.96%,Cgd-Vgd曲线误差Err:MAX=22.43%|RMS=3.001%。
[Abstract]:Power VDMOSU Vertical production Double-Diffused Metal Oxide Semicondu (Vertical double Diffusion Field effect Transistor) devices are one of the mainstream products of power electronics. VDMOS is widely used in many fields, such as switching power supply, motor drive, energy saving lamp and automotive electronic parts, because of its high input impedance, wide safe working area, fast switching speed and good thermal stability. China has made a lot of progress in the research of VDM OS devices, but it is not mature enough, and many VDMO S products need to be imported in our country. It is of great significance to explore the characteristics of power VDMOS devices, model establishment and model optimization. In this paper, a new generation of high voltage MOSFET products, S-RinTM series high voltage VDMOSs, has been developed by Shirawuer Microelectronics, which has been used in AC-DC power supply, DC-DC converters and PWM motor drivers. This paper briefly introduces the application and development prospects of VDMOS and the significance of model research, and summarizes the related theories of the model, including spice model and its development, as well as the characteristics of met model and the main device physics mechanism considered. Then it introduces the device testing system, model extraction software and the detailed and comprehensive model extraction steps, then introduces the structure development of power VDMOS and analyzes its DC characteristics, thermal temperature characteristics and dynamic capacitance characteristics. Finally, the DC and dynamic capacitance of VDMOS are tested, including output characteristic curve, transfer characteristic curve and I-V curve) and dynamic capacitance curve. Model extraction software is selected to model VDMOS. It was found that the initial met model could not be used to characterize the VDMOS devices because it was mainly transversely oriented MOSFET devices. Therefore, on the basis of met model, a resistance controlled by gate voltage and drain voltage is added to the drain of VDMOS, which can fit the test data of VDMOS well and improve the accuracy of the model. At the same time, some changes have been made in the VAAGA-VAilog-Amodel file of met model, and the original equation has been modified in Verilog-A code, and some parameters which are mainly used to fit the linear region and saturation region have been added. The simulation curve of the optimized met model is in accordance with the actual IV characteristics of VDMOS. For the solution of CV curve fitting, the paper mainly carries on a piecewise function approximation to the measured data, and then expresses the piecewise function in the form of subcircuit. Finally, the fitting degree of CV curve obtained by Cadence simulation is higher. The error of Id-Vg curve Err: MAX1 is 100% RMS16.96 and the error of Cgd-Vgd curve Err: MAXD 22.43% RMS3.001.
【学位授予单位】：杭州电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386

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