基于FPGA的高压信号源设计

发布时间：2018-06-27 15:42

本文选题：DDS + ROM　；参考：《河北大学》2015年硕士论文

【摘要】：在铁电材料研究中,铁电材料的极化和反转时需要较高的电压,因此要求具有高输出电压的信号源,目前市场上常规信号源输出电压一般为5Vpp,这显然不能满足实验室研究使用,针对于此问题,论文提出一种基于FPGA利用直接频率合成(DDS)技术开发任意波形高压源的方法。高压信号源的设计主要分为两个部分,一个是FPGA的任意波形发生器的开发,一部分是对任意信号升压并放大输出功率。任意波形发生器的设计是基于直接频率合成(DDS)技术在可编程逻辑器件上设计实现。论文在介绍DDS开发技术的基础上,给出了本系统在FPGA上总体设计方案,采用Verilog HDL硬件描述语言完成了DDS波形发生模块设计,结合设计中遇到ROM资源不够的问题,对DDS ROM压缩技术的应用与实现进行了重点研究与介绍,本设计分别针对正弦波、三角波对称性,锯齿波的单调性,方波的幅值只有0和1的特点做了不同的优化压缩设计,最终压缩比达到16:3,而硬件电路仅仅增加了一个计数器和一个反向器,解决了设计时FPGA ROM资源不够的问题。任意波形发生器的控制单元采用了SOPC技术,利用Nios II软核处理器实现对DDS波形发生模块、LCD液晶屏的控制,以及对键盘的控制信号的采集,在控制单元的设计上,论文重点分析了Nios II系统的HAL开发环境,给出了对LCD和键盘控制的流程图,并用C语言设计了相关程序。信号升压模块采用了浮动电压源技术,将普通运算放大器的输出电压从±15V升高至±20V,最终设计了运算放大器驱动的甲乙类功率放大器实现了功率放大的同时解决了甲乙类放大器的交越失真问题。最终测试结果表明,系统实现了频率0-1Mhz可调的正弦波、三角波、锯齿波及占空比可调的方波波形输出,信号理论分辨率可达0.023Hz,实测最小频率小于10Hz,输出峰峰值电压最高可达40Vpp。
[Abstract]:In the study of ferroelectric materials, the polarization and reversal of ferroelectric materials require high voltage, so the signal source with high output voltage is required. The current output voltage of the conventional signal source in the market is generally 5Vpp, which is obviously unable to be used in laboratory research. In this paper, a kind of FPGA based direct frequency synthesis (DD) is proposed in this paper. S) technology to develop arbitrary waveform high voltage source. The design of high voltage signal source is divided into two parts, one is the development of arbitrary waveform generator of FPGA, the other is to boost and amplify the output power of any signal. The design of arbitrary waveform generator is based on the design of direct frequency synthesis (DDS) technology on programmable logic devices. On the basis of introducing the DDS development technology, the paper gives the overall design scheme of this system on the FPGA, and uses the Verilog HDL hardware description language to complete the design of DDS waveform generation module. Combined with the problem of insufficient ROM resources in the design, the application and implementation of the DDS ROM compression technology are emphatically studied and introduced, and the design is divided into this design. The pin on the sine wave, triangle wave symmetry, the monotonicity of the sawtooth wave, the Fang Bo's amplitude only 0 and 1 characteristics do different optimal compression design, the final compression ratio reaches 16:3, and the hardware circuit only adds a counter and a reverse device, which solves the problem of insufficient FPGA ROM resources in the design. The unit uses the SOPC technology, uses the Nios II soft core processor to realize the DDS waveform generation module, the LCD LCD screen control, and the acquisition of the control signal of the keyboard. In the design of the control unit, the paper focuses on the HAL development environment of the Nios II system, gives the flow chart of the LCD and keyboard control, and designs the correlation with the C language. The signal boost module uses the floating voltage source technology to increase the output voltage of the ordinary operational amplifier from + 15V to + 20V. Finally, a class a class B power amplifier driven by an operational amplifier has been designed to achieve the power amplification and the problem of the crossings of the class a class B amplifier. The final test results show that the system is implemented. The frequency 0-1Mhz adjustable sine wave, triangular wave, sawtooth wave and square wave output with adjustable occupied space ratio, the theoretical resolution of the signal can reach 0.023Hz, the measured minimum frequency is less than 10Hz, and the maximum peak and peak voltage of the output can reach 40Vpp.
【学位授予单位】：河北大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN741;TN791

【参考文献】