12bit 200MSPS时间交织流水线ADC研究与设计

发布时间：2018-06-27 19:49

本文选题：模数转换器 + 时间交织　；参考：《华中科技大学》2015年硕士论文

【摘要】：随着先进的数字系统远远超越模拟电路,尤其是制造工艺线移向纳米级别后,最近十几年对高速、高精度、低功耗的模数转换器(ADC)的需求越来越迫切。流水线型模数转换器是从中频采样到高频采样并且具有高精度的典型结构。然而在深亚微米,低电源电压下设计一个高增益高带宽低功耗的运算放大器是比较困难的。为了避免这种限制,好几个流水线型模数转换器利用时间交织技术合并成一个整体的模数转换器的构想被提了出来。总体来说,时间交织流水线型模数转换器是复杂结构和能量利用率之间折中选择。基于以上考虑,本文采用SMIC 0.13um CMOS工艺设计了一款12位200MSPS的时间交织流水线型模数转换器。采用时间交织、流水线、运放共享等技术,既提高了速度和精度也节省了功耗。同时为了减小时序扭曲对时间交织流水线模数转换器性能的影响,提出了一种对时序扭曲不敏感的采样保持电路。本文首先对模数转换器的工作原理和典型的结构做了介绍;然后从系统结构、流水线型模数转换器和子模块的设计方面分析了实现12位200MSPS模数转换器的方案;最后给出了本文要求的高速高精度模数转换器的电路设计和仿真。仿真结果表明在采样速率为200MSPS,模拟输入信号频率为60MHz时无杂散动态范围可以达到88.8dB,信噪失真比为73.2dB,而功耗为107mW。
[Abstract]:With the advanced digital system far beyond analog circuits, especially after the manufacturing process line moves to nanometer level, the demand for high speed, high precision, low power ADC (ADC) is becoming more and more urgent in the last decade. Pipeline A / D converter is a typical structure with high precision from if sampling to high frequency sampling. However, it is difficult to design an operational amplifier with high gain, high bandwidth and low power consumption at deep submicron and low power supply voltage. In order to avoid this limitation, several pipelined analog-to-digital converters have been proposed to merge into a whole analog-to-digital converter using time interleaving technology. In general, time interleaving pipelined A / D converters are a trade-off between complex structures and energy utilization. Based on the above considerations, a 12 bit 200 MSPS time interleaving pipeline A / D converter is designed using SMIC 0.13um CMOS technology. Time interleaving, pipelining and operational amplifier sharing are used to improve speed and precision and save power consumption. In order to reduce the influence of time sequence distortion on the performance of time interleaving pipeline A / D converter, a sampling and holding circuit which is not sensitive to time sequence distortion is proposed. In this paper, the working principle and typical structure of A / D converter are introduced firstly, and then the scheme of 12 bit 200 MSPS ADC is analyzed from the aspects of system structure, pipeline ADC and sub-module design. At last, the circuit design and simulation of high-speed and high-precision A-D converter are given. The simulation results show that when the sampling rate is 200MSPS and the analog input signal frequency is 60MHz, the spurious dynamic range can reach 88.8dB, the signal-to-noise ratio is 73.2dB, and the power consumption is 107mW.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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