全并行—逐次逼近混合型模数转换器的设计与研究

发布时间：2018-06-27 22:36

  本文选题：全并行模数转换器 + 逐次逼近型模数转换器　； 参考：《合肥工业大学》2017年硕士论文

【摘要】：随着CMOS半导体工艺的迅速发展,数字信号处理技术得到了很大提高。相对于模拟信号,数字信号有着更高的可靠性、简便性以及灵活性等优点,因此数字信号处理已成为现代信号处理的主流方式。模数转换器(Analog-to-Digital,ADC)作为连接模拟信号和数字信号的纽带,需要先将自然界中的模拟信号转换成数字信号后,系统才能利用数字信号处理的方式处理模拟信号。因此,人们对ADC的需求越来越强烈,同时对其研究也日益受到关注。逐次逼近型(successive approximation register,SAR) ADC因其结构简单、功耗低、面积小等优点而获得广泛运用。基于传统结构的N比特SAR ADC每完成一次转换都需要进行N次比较,而每次的比较速度又受限于电容型数模转换器(Digital to Analog Converter,DAC)的建立时间和逻辑控制电路的传递延迟。因此,传统结构的这种缺陷阻碍了 SARADC向高速高精度领域的发展。全并行模数转换器(Flash ADC)由于结构和工作原理相对简单,因此其转换速度非常高。但是随着ADC位数的增加,其面积和功耗成指数型增长,因此给ADC的高精度设计带来了挑战。全并行—逐次逼近混合型模数转换器(Flash-SARADC)是一种将Flash ADC和SARADC各自的优点相结合的新型ADC结构,由于其在面积、速度、功耗以及精度方面具有较好的折中,因此得到了广泛的研究。本文首先对Flash-SAR ADC的工作原理和系统结构进行了阐述,同时详细分析了其结构中存在的非理想因素,并提出了相应的解决方案。接着,本文在对现有的开关策略进行分析和对比的基础上,提出了一种高位电容跳过与复用的开关策略,从而大幅度优化了电荷再分配型DAC的动态功耗和面积。相对于MCS开关策略,提出的开关策略使电容阵列所需的电容总数减小一半,电平切换功耗降低81.22%。然后,详细介绍了关键电路的设计,并给出了系统仿真结果。最后,本文采用SMIC0.18μmCMOS混合信号工艺设计了一款10位100MS/s Flash-SAR混合型ADC。所设计的ADC采用“3+8”的两极流水线结构,最后通过冗余位数字校准电路得到10位的量化精度。电路仿真结果表明:当采样信号的频率为100MS/s,输入信号的频率为48.14453125MHz的满幅正弦差分信号时的输出信号的无杂散波动态范围(SFDR)为75.879dB、信号噪声失真比(SNDR)为61.37dB、有效位数(ENOB)位9.902位;当采样频率为l00MS/s,输入信号频率为1.07421875MHz,工艺角为FF时,ADC的SFDR为78.669dB,SNDR为61.839dB,ENOB为9.980 bit;当工艺角为TT时,ADC的SFDR为 76.201dB,SNDR为61.15dB,ENOB为9.865bit;当工艺角为 SS 时,ADC 的 SFDR 为 76.937dB, SNDR 为 60.594dB, ENOB 为 9.773 bit。提出的Flash-SAR ADC在1.8V电源电压和Nyquist输入信号下,芯片功耗为 2.41mW,品质因数(Figure of merit, FOM)为 25.19fJ/conversion-step。
[Abstract]:With the rapid development of CMOS semiconductor technology, digital signal processing technology has been greatly improved. Compared with analog signal, digital signal has higher reliability, simplicity and flexibility, so digital signal processing has become the mainstream of modern signal processing. As the link between analog signal and digital signal, Analog-to-digital converter (ADC) needs to convert the analog signal into digital signal before the system can process the analog signal by digital signal processing. Therefore, the demand for ADC is becoming more and more intense, and the research on ADC has been paid more and more attention. Successive approximation (successive approximation register (successive approximation) ADC is widely used because of its simple structure, low power consumption and small area. The traditional N-bit Analog ADCs need to be compared for N times for each conversion, and the speed of each comparison is limited by the time of establishment of the digital to Analog converter and the transfer delay of the logic control circuit. Therefore, this defect of traditional structure hinders the development of SARADC to high speed and high precision. Full parallel analog-to-digital converter (Flash ADC) is very fast because of its simple structure and working principle. However, with the increase of ADC bits, its area and power consumption increase exponentially, which brings challenges to the high precision design of ADC. Full-parallel-successive approximation hybrid analog-to-digital converter (Flash-SARADC) is a new ADC structure which combines the advantages of Flash ADC and SARADC. Due to its good compromise in area, speed, power consumption and precision, it has been widely studied. In this paper, the working principle and system structure of Flash-SAR ADC are described, and the non-ideal factors in the structure are analyzed in detail, and the corresponding solutions are put forward. Then, based on the analysis and comparison of the existing switching strategies, this paper proposes a switching strategy with high capacitance skipping and multiplexing, which greatly optimizes the dynamic power consumption and area of charge redistribution DAC. Compared with the MCS switching strategy, the proposed switching strategy reduces the total capacitance required by half and the switching power consumption by 81.22. Then, the design of the key circuit is introduced in detail, and the simulation results are given. Finally, a 10-bit 100MS / s Flash-SAR hybrid ADCC is designed using SMIC 0.18 渭 m CMOS mixed signal technology. The designed ADC adopts a "38" two-pole pipeline structure. Finally, the quantization accuracy of 10 bits is obtained by the redundant bit digital calibration circuit. The circuit simulation results show that when the sampling signal frequency is 100ms / s and the input signal frequency is 48.14453125MHz, the output signal has a non-spurious wave dynamic range (SFDR) of 75.879dB, a signal-to-noise distortion ratio (SNDR) of 61.37dB and a significant bit (ENOB) of 9.902 bits. When the sampling frequency is 100 Ms / s, the input signal frequency is 1.07421875 MHz and the process angle is FF, the SFDR of the ADC is 78.669 dBN, SNDR is 61.839 dB ENOB is 9.980 bit, when the processing angle is TT, the SFDR of the ADC is 76.201dBSNDR 61.15 dB ENOB is 9.865 bit. when the processing angle is SS, the SFDR of the ADC is 76.937 dB, the SNDR is 60.594dB, and the ENOB is 9.773 bit. when the processing angle is SS, the SFDR of the ADC is 76.937dB, the SNDR is 60.594dB, and the ENOB is 9.773 bit. Under 1.8V supply voltage and Nyquist input signal, the proposed Flash-SAR ADC has a power consumption of 2.41 MW and a figure of merit (FOM) of 25.19fJ / conversion-step.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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