基于时域量化的逐次逼近型ADC研究与设计

发布时间：2018-06-29 01:25

本文选题：时域量化 + 逐次逼近　；参考：《电子科技大学》2015年硕士论文

【摘要】：随着通信行业、多媒体技术和数字化设备的快速发展,ADC作为模拟世界和数字世界沟通的桥梁,其性能向高速、高精度、低功耗方向发展。深亚微米工艺下数字电路的优势在于高速、低功耗,因此将数字电路的优势应用在模数转换器的设计中更能够使其适应发展需求。本文采用55 nm CMOS工艺,通过对各种结构ADC以及混合结构ADC的优缺点进行研究和分析,设计了一款基于时域量化的10位100MS/s逐次逼近型ADC。首先,模拟电路的发展趋势之一是改变信号的表征方式,为了实现信号的时域表征,本文详细分析了时域量化的核心电路,包括电压时间转换器VTC、时间数字转换器TDC。通过对这两个核心电路的分析和比较提出了本文中采用的时域量化电路结构,其中VTC电路采用脉宽调制结构实现了输入信号轨到轨量化,TDC电路采用D触发器型和延迟线型组成的混合型结构实现了8位温度计编码输出,编码电路采用N中取1码编码方式实现了4位二进制量化结果输出以及DAC阵列开关相应位控制编码输出。同时对该电路中存在的失配、误差进行了研究和分析,通过利用时域量化冗余位提出了一种电路自校正方式。其次,为了实现高速、低功耗的目的,本文中采样开关采用栅压自举结构保证采样线性度,DAC阵列采用分段式电容分裂结构,减小了芯片面积和功耗,比较器采用低回踢噪声钟控比较器结构,并对比较器的失配进行校正、对等效输入噪声的影响进行分析。同时针对传统逐次逼近寄存器电路中存在延迟过大难以实现高速工作的特点提出了一种新型的逐次逼近寄存器结构,该结构采用锁存器实现移位功能,有效提高了电路工作速度,同时降低功耗。最后,基于55 nm CMOS工艺完成各个关键单元电路以及整体基于时域量化SAR ADC性能仿真验证。为了更好地与实际结果相符,在仿真过程中对关键电路以及关键节点添加寄生参数。仿真结果表明:在采样频率为100MHz,输入信号频率为22.65625MHz的条件下,ADC的信号噪声失真比SNDR为61.1070dB,无杂散动态范围SFDR为71.0713dB,有效位ENOB为9.8583位,优值FoM为39.2fJ/conversation-step,该性能满足设计要求。本文中所设计的ADC在1.2V的电源电压下功耗为3.65mW。
[Abstract]:With the rapid development of multimedia technology and digital equipment, ADC, as a bridge between analog world and digital world, is developing to high speed, high precision and low power consumption. The advantage of digital circuit in deep submicron technology lies in its high speed and low power consumption. Therefore, the advantage of digital circuit can be applied to the design of A / D converter to meet the needs of development. In this paper, the advantages and disadvantages of various ADC and hybrid ADC are studied and analyzed in 55nm CMOS technology. A 10-bit ADCs successive approximation based on time-domain quantization is designed. Firstly, one of the development trends of analog circuits is to change the signal representation. In order to realize the time domain representation, the core circuits of time domain quantization are analyzed in detail in this paper, including voltage time converter VTC and time digital converter TDC. Based on the analysis and comparison of the two core circuits, the time-domain quantization circuit structure used in this paper is proposed. The VTC circuit uses pulse width modulation structure to realize the input signal rail to rail quantization TDC circuit using the mixed structure of D flip-flop and delay line to realize 8-bit thermometer coding output. The 4-bit binary quantization result output and the DAC array switch corresponding bit control coding output are realized by using the 1-code encoding mode of N in the coding circuit. At the same time, the mismatch and error in the circuit are studied and analyzed, and a circuit self-tuning method is proposed by using redundant bits in time domain quantization. Secondly, in order to achieve the purpose of high speed and low power consumption, the sampling switch in this paper adopts the gate voltage bootstrap structure to ensure the sampling linearity degree DAC array to adopt the segmented capacitor split structure, which reduces the chip area and the power consumption. The comparator adopts the structure of low return kick noise clock controlled comparator, corrects the mismatch of the comparator, and analyzes the effect of equivalent input noise. At the same time, a new structure of successive approximation register is proposed, which uses latch to realize shift function, aiming at the characteristic that the delay is too big to work at high speed in the traditional successive approximation register circuit. The circuit speed is improved and the power consumption is reduced. Finally, every key cell circuit is completed based on 55nm CMOS process, and the performance of SAR ADC based on time domain quantization is verified by simulation. In order to better agree with the actual results, parasitic parameters are added to the key circuits and key nodes in the simulation process. The simulation results show that when the sampling frequency is 100 MHz and the input signal frequency is 22.65625 MHz, the signal noise distortion ratio of ADC is 61.1070dB, the SFDR is 71.0713dB, the effective bit ENOB is 9.8583 bits, and the excellent value FoM is 39.2 f / conversation step. The performance meets the design requirements. The ADC designed in this paper has a power consumption of 3.65 MW at 1.2V power supply voltage.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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