一种基于FPGA的低开销可重构容错系统设计

发布时间：2018-06-29 09:34

本文选题：FPGA + 可重构　；参考：《合肥工业大学》2015年硕士论文

【摘要】：由于FPGA在电路设计中,具有高度灵活性以及高效性,其应用变得越来越广泛。SRAM型FPGA具有性能好、密度高、成本低、可编程效果突出等优点,运用FPGA设计电路能够有效地缩短设计周期、降低设计成本,并且可以在轨修改设计,备受空间应用设计者的高度青睐。但是由于FPGA本身的结构功能特点,易遭受外界的影响(如辐射、高能粒子轰击等),使其产生翻转,造成电路结构和功能性错误及引发故障。对于环境条件恶劣的太空环境,如果不采取一定措施对FPGA电路进行容错加固,其可靠性将得不到保障,一旦发生故障有可能带来灾难性的后果。FGPA动态可重构功能的出现及应用,则为提高FPGA电路的可靠性提供了有效的解决方案。目前,FPGA的动态可重构技术已经越趋成熟,基于FPGA的高可靠性容错系统设计的研究具有重要意义。FPGA的容错加固不可避免的会带来额外的硬件资源开销和时间开销。为了降低系统的生产成本以及保持系统运行的连续性,应在保障可靠性的前提下,尽可能降低系统的硬件资源开销及时间开销。本文在基于FPGA的动态可重构技术的基础上,提出了一种低开销的容错系统设计方案,主要工作如下：(1)分析了FPGA在恶劣环境下发生错误的原因及危害,同时阐明了相关的常用容错加固技术。(2)在前人研究的基础上,提出了一种低开销的可重构容错系统的设计方案,采用双模冗余作为加固手段、以校验配置位作为故障定位措施、以动态重配置作为故障修复方法。(3)通过电路实现,计算并得出系统硬件资源开销大小,并与其它可重构容错系统做开销对比。在对比结果中,本文系统在保持可靠性和较低时间开销的基础上,进一步将系统硬件资源开销降低了140slices。
[Abstract]:Because FPGA has high flexibility and high efficiency in circuit design, it has become more and more widely used in SRAM type FPGA with good performance, high density, low cost, outstanding programmable effect and so on. Using FPGA to design the circuit can effectively shorten the design cycle, reduce the design cost, and can modify the design in orbit, which is highly favored by space application designers. However, FPGA is vulnerable to external influence (such as radiation, high-energy particle bombardment, etc.) because of its structural and functional characteristics, which makes it flip, causing circuit structure and functional errors and causing faults. The reliability of FPGA circuits will not be guaranteed if some measures are not taken to strengthen the fault-tolerant FPGA circuits in the space environment with poor environment conditions. Once the failure occurs, it may bring disastrous consequences. The appearance and application of FGPA dynamic reconfigurable function. It provides an effective solution for improving the reliability of FPGA circuit. At present, the dynamic reconfigurable technology of FPGA has become more and more mature. The research on the design of high reliability fault-tolerant system based on FPGA is of great significance. The fault-tolerant reinforcement of FPGA will inevitably bring additional hardware resources and time overhead. In order to reduce the production cost of the system and maintain the continuity of the system operation, the hardware resource and time cost of the system should be reduced as much as possible under the premise of ensuring the reliability. On the basis of the dynamic reconfigurable technology based on FPGA, this paper proposes a low overhead fault-tolerant system design scheme. The main work is as follows: (1) the causes and harm of FPGA errors in bad environment are analyzed. At the same time, some commonly used fault-tolerant reinforcement techniques are expounded. (2) based on the previous researches, a design scheme of a low-overhead reconfigurable fault-tolerant system is proposed, in which dual-mode redundancy is used as reinforcement method and checkout bit is used as fault location measure. Dynamic reconfiguration is used as the fault repair method. (3) the hardware resource overhead of the system is calculated by circuit and compared with that of other reconfigurable fault-tolerant systems. The comparison results show that the hardware resource overhead of the system is further reduced by 140 slices on the basis of maintaining reliability and low time cost.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791

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