基于多位触发器技术的SoC低功耗设计与实现

发布时间：2018-06-29 19:59

本文选题：SoC设计 + 时钟复用　；参考：《国防科学技术大学》2015年硕士论文

【摘要】：随着半导体产业的快速发展和集成电路工艺尺寸的缩小,SoC(System on Chip)芯片设计包含的内容越来越广泛,集成度也越来越高,功耗问题成了如今芯片设计中性能、封装、制冷和设备安全的制约因素;而且,随着以电池为主要供电方式的便携式和小型化设备需求的增加,电池技术的发展滞后于集成电路的快速发展也促进了低功耗设计需求。因此,系统芯片的低功耗设计是人们在评估芯片面积、成本以及性能的同时,需要综合考虑的重要问题。在当前的集成电路系统设计中,运用广泛而且有效的低功耗技术有:多阈值电压技术、电源关断技术、时钟关断技术、网表优化技术以及多电压供电技术等。芯片正常工作的时候,动态功耗占总功耗的90%以上,时钟路径上的动态功耗占系统总功耗的40%左右。因此,本论文针对一个设计项目进行分析,优先确定并使用了时钟关断技术、网表优化技术以及多电压供电技术,但仍不能完成本设计项目对低功耗设计更高标准的要求。最后根据对设计项目功能结构的具体分析得出:通过时钟复用的方法用多位触发器代替一位触发器可以有效地降低时钟路径上的动态功耗、减少单元面积,达到了低功耗设计标准。本论文主要优化设计了多位触发器,并有效的应用到了实际设计项目中,且在不违反新工艺的设计规则下,主要进行了以下工作:首先,使用时钟复用的方法分析设计了多位触发器的电路,并设计出完整的GDSII(Graphic Database System II)版图。从版图中抽取器件之间的寄生参数(包括电阻和电容),分析了多位触发器的性能并比较了多位触发器单元的优势。根据多位触发器的结构,定制出包含有时序信息和功耗信息的单元库。其次,对于常用的芯片设计流程,工具并不能准确的应用多位触发器,基于对数据路径的分析,在网表综合阶段通过路径映射的方法将多位触发器加入到芯片的逻辑结构中,在布局布线阶段修正掉设计规则的违例,在最终分析阶段对芯片进行逻辑分析和功耗时序分析。最后,在系统设计中通过使用自主设计的多位触发器并结合其他的低功耗技术,从而将功耗降低了36%,达到了最初要求的35%的标准。本论文的研究已取得了很好的成果,并应用到实际的设计项目中。
[Abstract]:With the rapid development of semiconductor industry and the reduction of integrated circuit process size, SoC (system on Chip) chip design contains more and more contents, and the integration level is becoming higher and higher. With the increasing demand for portable and miniaturized devices with battery as the main mode of power supply, the development of battery technology lags behind the rapid development of integrated circuits, which also promotes the demand for low-power design. Therefore, the low power design of the system chip is an important issue to be considered when evaluating the chip area, cost and performance. In the current integrated circuit system design, the widely used and effective low-power technologies include multi-threshold voltage technology, power off technology, clock turn off technology, network meter optimization technology and multi-voltage power supply technology. When the chip works normally, the dynamic power consumption accounts for more than 90% of the total power consumption, and the dynamic power consumption on the clock path accounts for about 40% of the total power consumption of the system. Therefore, this paper analyzes a design project, prioritizes and uses clock turn-off technology, network table optimization technology and multi-voltage power supply technology, but still can not meet the design project for a higher standard of low-power design. Finally, according to the concrete analysis of the function structure of the design project, it is concluded that the dynamic power consumption on the clock path can be effectively reduced and the cell area can be reduced by using multi-bit trigger instead of one bit trigger by the method of clock multiplexing. The design standard of low power consumption is reached. This paper mainly optimizes the design of multi-bit trigger, and applies it to the actual design project effectively, and under the condition of not violating the design rules of the new process, the main work is as follows: first, The circuit of multi-bit trigger is analyzed and designed by using clock multiplexing method, and a complete layout of GDSII (graphic Database system II) is designed. The parasitic parameters (including resistors and capacitors) between devices are extracted from the layout. The performance of multi-bit flip-flop is analyzed and the advantages of multi-bit flip-flop cells are compared. According to the structure of multi-bit trigger, the cell library which contains timing information and power information is customized. Secondly, for the commonly used chip design flow, the tool can not use the multi-bit trigger accurately. Based on the analysis of the data path, the multi-bit trigger is added to the logic structure of the chip through the path mapping method in the synthesis stage of the network table. In the layout and routing phase, the design rule violation is corrected, and the chip logic analysis and power sequence analysis are carried out in the final analysis stage. Finally, by using self-designed multi-bit flip-flop and other low-power technologies in the system design, the power consumption is reduced by 36%, and the standard of 35% is reached. The research of this paper has obtained very good result, and applied to the actual design project.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47

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