无线传感器网络射频频率综合器中关键模块的设计

发布时间：2018-07-02 09:08

  本文选题：无线传感器网络 + 锁相环　； 参考：《东南大学》2015年硕士论文

【摘要】：随着无线通信技术的不断发展,无线传感器网络(Wireless Sensor Network, WSN)将会逐渐成熟,其在信息感知领域的巨大价值使其备受国际科技界的关注。随着无线传感器网络的发展,对射频收发芯片的要求越来越高。本文研究的内容是无线传感网锁相环频率综合器中的小数分频器和自动频率校正AFC电路。本文设计了应用于WSN射频频率综合器中的二分频器、三分频器、可编程分频器、EA调制器和自动频率校准电路,所有电路基于TSMC0.18μm CMOS工艺,工作电压为1V。其中二分频器采用平行电流开关源极耦合逻辑结构；三分频器采用双沿触发器环形连接,保证输出占空比为50%;可编程分频器采用双模预分频器和PS计数器结构,实现速率与功耗的平衡,PS计数器采用全定制设计方法,提高工作频率使得可使用分频器较小的预分频器,减小整个可编程分频器的最小连续分频比：ΣA调制器采用改进的MASH 1-1-1结构,由三个一阶误差反馈调制器(Error Feedback Modulator, EFM)级联构成,并在相邻两个EFM之间增加一个前馈连接,最终达到减小小数杂散的目的；自动频率校准电路采用开环工作的频率检测方案,在工作时间和电路复杂度之间取得平衡,符合本系统要求。后仿真结果表明,在电源电压为1V,温度为27。tt工艺角下,二分频器工作频率范围为4～8GHz,输入信号频率为5GHz时对应的输出信号正交误差约0.310,正交性良好；三分频器的工作频率范围为0.5～4.5GHz,占空比为50%；可编程分频器的工作频率范围为1.0～6.5GHz,在最高工作频率时功耗为3.99mW;∑△调制器输入20位分频比的小数位,输出3位动态分频比,工作正常,与可编程分频器联合工作正确实现小数分频,工作频率范围为1.0-6.5GHz,分频比范围为186.72-221.76,频率分辨率为24Hz,核心功耗不超过4.8mmW。本文设计的可编程分频器进行了流片,得到最终测试结果为：芯片面积为0.675mm X 0.378mm,可编程分频器工作频率范围为0.5～6.0GHz,在6.0GHz下的功耗为3.48mW。测试结果满足设计指标。本文所设计的各个模块满足WSN系统的要求,并且具有低功耗的特点,预期可以应用到WSN核心芯片中。
[Abstract]:With the continuous development of wireless communication technology, Wireless Sensor Network (WSN) will gradually mature, and its great value in the field of information perception has attracted the attention of the international science and technology community. With the development of wireless sensor networks, RF transceiver chips are required more and more. The content of this paper is the fractional frequency divider and the automatic frequency correction AFC circuit in the phase locked loop frequency synthesizer of the wireless sensor network. In this paper, two divider, three frequency divider, programmable frequency divider EA modulator and automatic frequency calibration circuit used in WSN RF frequency synthesizer are designed. All circuits are based on TSMC 0.18 渭 m CMOS technology and the working voltage is 1V. The two-frequency divider adopts parallel current switch source polar coupling logic structure, the three-frequency divider adopts double-edge trigger annular connection to ensure the output duty cycle is 50, the programmable frequency divider adopts dual-mode predivider and PS counter structure. The balanced PS counter, which realizes speed and power consumption, adopts a fully customized design method, which increases the working frequency so that a predivider with smaller frequency divider can be used. Reducing the minimum continuous frequency ratio of the whole programmable frequency divider: 危 A modulator adopts an improved MASH1-1-1 structure, which consists of three first-order error feedback modulator (EFM) cascades, and adds a feedforward connection between two adjacent EFM. The automatic frequency calibration circuit uses open-loop frequency detection scheme to achieve a balance between working time and circuit complexity, which meets the requirements of the system. The simulation results show that when the power supply voltage is 1V and the temperature is 27.tt process angle, the frequency range of the frequency divider is 4g / 8GHz, and the quadrature error of the output signal is about 0.310 when the input signal frequency is 5GHz, and the orthogonality is good. The operating frequency range of the three divider is 0.5 ~ 4.5GHz, the duty cycle is 50GHz, the working frequency range of the programmable divider is 1.0 ~ 6.5GHz, and the power consumption is 3.99mW at the highest operating frequency. The 鈭，

本文编号：2089630