基于多栅晶体管结构的60GHz CMOS功率放大器的设计及实现

发布时间：2018-07-03 01:55

本文选题：60GHz + 多栅晶体管结构　；参考：《东南大学》2015年硕士论文

【摘要】：当今社会的高速发展使得人们对短距离无线通信的数据传输速度提出了越来越高的要求。由于极大带宽等一系列优点,60GHz频段无线通信系统可以达到Gb/s的通信速度,这使它能够比较好地应用在短距离无线通信场合。然而,在这么高的频段上,基于CMOS工艺的全集成收发系统,特别是其中的功率放大器模块设计难度很大。从文献调研结果来看,功率合成技术和中和电容技术的使用提高了60GHz CMOS功率放大器的输出功率和增益等性能。但是,在实际应用当中具有重要意义的线性度和功率回退效率却还没有取得大的发展,这为60GHz频段的大规模应用设置了障碍。面对以上挑战,本文在变压器匹配和中和电容技术的基础上进行创新,在功率放大器设计中采用了一种新型的复合式结构——多栅晶体管结构。理论分析显示,该结构能在几乎不改变整体电路功耗的前提下同时实现线性度和回退效率的提升,有效突破这两个指标的制约。为了验证这个结构的实际效果,本文采用65nm CMOS工艺设计并实现了一款60GHz两级差分功率放大器,芯片面积为0.49mm2。测试结果显示,在1V的供电电压之下,电路的静态功耗为24mW。当电路工作在54GHz时,输出饱和功率和1dB压缩点分别达到了10.5dBm和7.62 dBm。与公开文献相比,这是同等功耗的电路中输出功率性能最好的。与之对应,电路的最大效率和1dB压缩时的效率分别为23.3%和16.98%,这也是目前已发表结果中较优的。在51～56GHz的范围内,1dB压缩点处的效率均大于8%。
[Abstract]:With the rapid development of the society, the data transmission speed of short-range wireless communication is demanded more and more. Due to a series of advantages, such as the maximum bandwidth, the wireless communication system in the 60GHz band can achieve the communication speed of GB / s, which makes it suitable for short range wireless communication. However, in such a high frequency band, it is very difficult to design a fully integrated transceiver system based on CMOS technology, especially the power amplifier module. The results show that the use of power combination technology and neutralization capacitor technology can improve the output power and gain of 60GHz CMOS power amplifier. However, the linearity and power back efficiency, which are of great significance in practical applications, have not yet made great progress, which poses an obstacle to the large-scale application of the 60GHz band. Facing the above challenges, this paper innovates on the basis of transformer matching and neutralizing capacitor technology, and adopts a new compound structure, multi-gate transistor structure, in the design of power amplifier. Theoretical analysis shows that the proposed structure can achieve the improvement of linearity and recovery efficiency at the same time without changing the power consumption of the whole circuit effectively breaking through the constraints of these two indexes. In order to verify the practical effect of this structure, a 60GHz two-stage differential power amplifier is designed and implemented using 65nm CMOS technology. The chip area is 0.49mm ~ 2. The test results show that the static power consumption of the circuit is 24 MW at 1 V supply voltage. When the circuit operates at 54GHz, the output saturation power and 1dB compression point are 10.5dBm and 7.62dBmrespectively. Compared with the open literature, this is the best output power performance in circuits with equal power consumption. The maximum efficiency of the circuit and the efficiency of 1dB compression are 23. 3% and 16. 98% respectively. The efficiency of 1 dB compression point is greater than 8 in the range of 51 ~ 56 GHz.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN722.75

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