当前位置:主页 > 科技论文 > 电子信息论文 >

150V抗辐射VDMOS的设计

发布时间:2018-07-07 17:07

  本文选题:VDMOS + 抗辐射 ; 参考:《东南大学》2015年硕士论文


【摘要】:随着信息技术产业的迅猛发展,功率器件可靠性和抗恶劣环境能力已然成为现代化军事及航空航天等领域的重要研究课题。抗辐射加固器件的低需求量与工艺线特殊性致使其电学性能落后于同时代商业产品。因此,研究功率器件的辐射效应并设计与现代化生产线兼容的抗辐射器件生产工艺流程意义重大。本文首先在VDMOS基本结构与工艺流程研究的基础上,针对器件不同工作状态分析了相应的物理模型,讨论了VDMOS击穿电压、阈值电压和导通电阻的计算方法,并简要探讨了场限环和场板在终端结构中的应用。其次,在SEB辐射效应的一维分析模型和二维数值仿真模型基础上,讨论了CIA效应与三极管击穿特性的关系。综合考虑VDMOS的寄生三极管及CIA电流放大系数,提出了拟光触发晶闸管模型与新的SEB临界条件。利用仿真软件MEDICI验证了SEB的电压特性与位置关系,得出了器件的SEB敏感区域为沟道与外延层边界,并指出了颈区的特殊性。基于颈区附近SEB电流响应中由栅漏电流引起的SEB塌陷现象,提出了全新的栅致单粒子烧毁(SEGIB)模型,解释了传统SEB效应与栅漏电流对该区域SEB现象的共同影响,并用因子γSG表征这一影响的大小。然后,在原有SEB数值仿真判定模型基础上,提出了新的SEB复合判定法,将器件的SEB电流响应与击穿特性相结合,利用交点电压精确判定抗辐射能力。对这种复合判定法进一步优化后,结合器件辐射敏感区域,提出了SOLA点与S参数以表征器件的SEB加固能力的方法,并用此方法对常见辐射加固措施进行研究,发现局部SOI与沟槽结构抗SEB能力较好,超结结构无明显作用,梯度外延与P+扩散有一定效果。最后,基于指标要求设计了VDMOS的尺寸与工艺,选择后栅工艺、梯度外延、P-扩散作为兼容现有生产工艺的抗辐射加固措施,并绘制版图。仿真结果显示该器件击穿电压155V,阈值电压3.2V,额定电流大于20A,导通电阻0.05 Ω并有较好的抗辐射能力,满足设计要求。
[Abstract]:With the rapid development of information technology industry, the reliability of power devices and the ability to resist adverse environment have become an important research topic in modern military, aerospace and other fields. The low demand for radiation hardening devices and the particularity of the process line make their electrical properties lag behind the commercial products of the same era. Therefore, it is of great significance to study the radiation effect of power devices and design the production process of anti-radiation devices compatible with modern production line. Based on the research of VDMOS basic structure and process flow, the physical models of VDMOS are analyzed in different working states, and the calculation methods of breakdown voltage, threshold voltage and on-resistance are discussed. The application of field limiting ring and field plate in terminal structure is briefly discussed. Secondly, based on the one-dimensional analysis model and two-dimensional numerical simulation model of SEB radiation effect, the relationship between the CIA effect and the breakdown characteristics of the transistor is discussed. Considering the parasitic transistor and CIA current magnification factor of VDMOS, a quasi-light-triggered thyristor model and a new SEB critical condition are proposed. The relationship between the voltage characteristics and the position of SEB is verified by the simulation software Medici. The sensitive region of SEB is found to be the boundary of channel and epitaxial layer, and the particularity of the neck region is pointed out. Based on the SEB collapse caused by gate leakage current in the SEB current response near the neck region, a new gate induced single particle burn (SEGIB) model is proposed, which explains the joint effect of the traditional SEB effect and the gate leakage current on the SEB phenomenon in this region. The effect was characterized by factor 纬 SG. Then, based on the original SEB numerical simulation decision model, a new SEB compound decision method is proposed, which combines the current response of the SEB device with the breakdown characteristics, and uses the intersection voltage to accurately determine the anti-radiation ability. After further optimization of the composite decision method, a new method of Sola point and S parameter is proposed to characterize the SEB reinforcement ability of the device, and the common radiation reinforcement measures are studied by using this method, which combines the radiation sensitive region of the device with the SOLA point and the S parameter to characterize the SEB reinforcement ability of the device. It is found that the local SOI and grooved structure have better anti-SEB ability, but the superjunction structure has no obvious effect. Gradient epitaxy and P-diffusion have some effect. Finally, the size and process of VDMOS are designed based on the index requirements. The back gate process and gradient epitaxial P- diffusion are selected as the anti-radiation reinforcement measures compatible with the existing production process, and the layout is drawn. The simulation results show that the device has a breakdown voltage of 155V, a threshold voltage of 3.2V, a rated current of more than 20A, a on-resistance of 0.05 惟 and a good radiation resistance, which meets the design requirements.
【学位授予单位】:东南大学
【学位级别】:硕士
【学位授予年份】:2015
【分类号】:TN386

【相似文献】

相关期刊论文 前10条

1 唐昭焕;胡刚毅;陈光炳;谭开洲;刘勇;罗俊;徐学良;;A novel structure for improving the SEGR of a VDMOS[J];半导体学报;2012年04期

2 王英;何杞鑫;方绍华;;高压功率VDMOS管的设计研制[J];电子器件;2006年01期

3 杨东林;孙伟锋;刘侠;;700V VDMOS设计[J];电子器件;2007年02期

4 刘侠;孙伟锋;王钦;杨东林;;高压VDMOS电容的研究[J];电子器件;2007年03期

5 蔡小五;海潮和;王立新;陆江;;新型低压超结功率VDMOS器件数值模拟[J];功能材料与器件学报;2007年05期

6 徐丹;殷景华;王鑫宇;;VDMOS器件微观结构研究[J];应用科技;2007年11期

7 刘刚;蔡小五;韩郑生;陆江;王立新;夏洋;;国产VDMOS电离辐射环境中的敏感参数研究[J];核技术;2008年08期

8 谭开洲;胡刚毅;杨谟华;徐世六;张正t,

本文编号:2105644


资料下载
论文发表

本文链接:https://www.wllwen.com/kejilunwen/dianzigongchenglunwen/2105644.html


Copyright(c)文论论文网All Rights Reserved | 网站地图 |

版权申明:资料由用户e9407***提供,本站仅收录摘要或目录,作者需要删除请E-mail邮箱bigeng88@qq.com