基于划分的三维布局器的设计与实现

发布时间：2018-07-08 12:20

本文选题：布局 + 三维集成电路　；参考：《国防科学技术大学》2015年硕士论文

【摘要】：随着集成电路技术不断发展,互连问题成为影响芯片性能的瓶颈。三维集成电路技术提供给设计者一种全新的设计方式,能够有效地缩短互连线长、降低时序延迟、改善芯片性能,目前已成集成电路发展的新方向。在三维芯片设计过程中,布局是物理设计中重要的环节,但是目前国际范围内还缺乏有效支持三维芯片设计的EDA工具,因此研究突破三维芯片布局技术对提高芯片的性能具有重要意义。与传统二维芯片相比,三维芯片具有特殊的三维结构,因此三维芯片设计不能简单地照搬二维芯片的设计技术,其布局问题需要研究开发新的三维布局算法。本文结合国内外布局算法研究动态,选取三维芯片布局技术作为研究方向。首先对国际物理设计会议提供的二维benchmark进行研究,并且设计实现基于折叠的三维转换方法,将二维benchmark转换为三维benchmark,将其作为三维布局算法研究的基础。然后设计实现一个基于划分的三维布局器,完成三维芯片上的布局,并对布局结果的互连线长进行性能评估。结果表明:第一,相对于“Krafwerk”二维布局算法,基于划分的三维布局器HPWL平均减少35.02%。第二,相对于基于折叠的三维布局器,基于划分的三维布局器HPWL平均减少26.60%,运行时间平均减少26.81%。基于划分的三维布局器的实现将会为我国自主研发三维芯片提供相应的理论和技术支持。
[Abstract]:With the development of integrated circuit technology, interconnection becomes the bottleneck of chip performance. Three-dimensional integrated circuit technology provides designers with a new design method, which can effectively shorten the interconnection line length, reduce timing delay, improve chip performance, has become a new direction of integrated circuit development. In the process of 3D chip design, layout is an important part of physical design, but there is still a lack of EDA tools to support 3D chip design in the international scope. Therefore, it is important to research and break through the three-dimensional chip layout technology to improve the chip performance. Compared with traditional 2D chips, 3D chips have special 3D structure, so 3D chip design can not simply copy the design technology of 2D chips. The layout problem of 3D chips needs to be studied and developed. In this paper, three-dimensional chip layout technology is selected as the research direction, combined with the research trends of layout algorithms at home and abroad. Firstly, the 2D benchmark provided by the International physical Design Conference is studied, and the folding based 3D conversion method is designed and implemented. The 2D benchmark is converted to 3D benchmark, which is the basis of the research on 3D layout algorithm. Then we design and implement a 3D layout device based on partition to complete the layout of 3D chip and evaluate the performance of the interconnect length of the layout result. The results show that: first, compared with the "Krafwerk" two-dimensional layout algorithm, the average reduction of HPWL based on partition is 35.02. Second, compared with the folding based 3D layouts, the partition based 3D layouts reduce the average HPWL by 26.60 and the average running time by 26.81. The realization of 3D layout based on partition will provide corresponding theoretical and technical support for our own research and development of 3D chips.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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