低相位噪声CMOS集成压控振荡器的设计

发布时间：2018-07-08 18:50

本文选题：压控振荡器 + 相位噪声　；参考：《湖南大学》2015年硕士论文

【摘要】：随着现代通信技术的日益发展,特别是无线通信技术的全面推广,电子通信系统延续了高性能、低成本、集成化的发展趋势,而压控振荡器又是无线通信技术最核心的部分,电子设备对压控振荡器的技术指标要求越来越高。传统的分立压控振荡器功耗高、频率范围低且带宽窄,与集成芯片之间的寄生参数大,这些都限制了它无法满足现代无线的技术指标;而目前集成压控振荡器已经能够集成,性能优秀,但是与CMOS集成压控振荡器相比,有两个明显的不足:一是工艺成本高,如果整个系统都采用此类工艺(诸如砷化镓工艺、双极型工艺、Bi Cmos工艺),将使得产品的造价成倍的上升,难以实现批量生产;二是使用的不是CMOS工艺,与后端数字电路不兼容,也就难以进行系统级芯片设计(System On Chip)。现在的客户都追求小、精、廉的价值观念,为了适应客户的需求以及电子技术的主流发展趋势,设计一款低相噪、宽频域、低功耗的CMOS工艺的集成压控振荡器,易于进行系统级芯片设计,大幅提高整个产品的性能,使产品做到真正的物美价廉,已是电子通信技术发展的必然走向。基于设计压控振荡器的基本理论,结合国内外的研究现状,设计出了一款低相位噪声、宽频域CMOS集成压控振荡器。论文首先简单的介绍了压控振荡器的发展状况,并提出了相应的一些技术指标和要求,然后对集成压控振荡器的设计做出了分析,这些分析主要包括集成压控振荡器常用结构的特点、拓扑的选择及LC振荡器中变容管和片上电感的设计要求等等。论文重点介绍了低相位噪声和宽频域调谐的压控振荡器的设计,对平面螺旋电感进行了优化和对MOS变容管进行了参数设计,通过建立压控振荡器的小信号等效模式,确立了设计参数。论文对压控振荡器的其他相关电路模块也进行了简单的分析。主要工作成果有:谐振回路无源器件的片上实现,对无源器件的闪烁噪声进行重点优化,降噪技术为二次谐波谐振技术和感性压控端技术。电路设计采用SMIC 0.18μm CMOS射频工艺,利用Cadence软件的Spectre RF工具仿真,仿真结果为:中心频率为2.00 GHz,输出频率为1.85 GHz到2.15 GHz,调谐范围为15%,相位噪声为-120 d Bc/@1MHz,静态功耗为0.72 m W。完全达到了设计要求。
[Abstract]:With the development of modern communication technology, especially the popularization of wireless communication technology, electronic communication system continues the development trend of high performance, low cost and integration, and voltage controlled oscillator is the core part of wireless communication technology. The technical requirements of VCO are becoming higher and higher in electronic equipment. The traditional discrete voltage controlled oscillator has high power consumption, low frequency range and narrow bandwidth, and large parasitic parameters with the integrated chip, which limit it to meet the technical requirements of modern wireless, but the integrated voltage controlled oscillator has been able to integrate. Performance is excellent, but there are two obvious disadvantages compared to CMOS integrated VCO: one is the high cost of the process, if the whole system uses such a process (such as gallium arsenide process, Gallium arsenide process), The bipolar process (Bi CMOS process) will double the cost of the product and make it difficult to realize batch production. Second, it is difficult to design system on Chip because it is not a CMOS process and is incompatible with the back end digital circuit. In order to meet the needs of customers and the mainstream trend of electronic technology, we design an integrated VCO with low phase noise, wide frequency domain and low power consumption in CMOS process. It is an inevitable trend of the development of electronic communication technology that it is easy to design system-level chips, greatly improve the performance of the whole product, and make the products really good and cheap. Based on the basic theory of designing VCO, a low phase noise, broadband CMOS integrated VCO is designed. Firstly, the development of VCO is briefly introduced, and some technical specifications and requirements are put forward, then the design of integrated VCO is analyzed. These analyses mainly include the characteristics of the common structure of the integrated VCO, the choice of topology and the design requirements of the varactor and on-chip inductor in the LC oscillator. This paper mainly introduces the design of VCO with low phase noise and wide frequency domain tuning, optimizes the planar spiral inductor and designs the parameters of MOS varactor. The small signal equivalent mode of VCO is established. The design parameters are established. The other circuit modules of VCO are also analyzed in this paper. The main results are as follows: the on-chip realization of the passive devices in the resonant circuit, the optimization of the scintillation noise of the passive devices, the second harmonic resonance technology and the inductive voltage-controlled terminal technology are used to reduce the noise. The circuit is designed in SMIC 0.18 渭 m CMOS RF process. The simulation results are as follows: the center frequency is 2.00 GHz, the output frequency is 1.85 GHz to 2.15 GHz, the tuning range is 15x, the phase noise is -120 d Bc / r -1MHz, and the static power consumption is 0.72 MW. Fully meet the design requirements.
【学位授予单位】：湖南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN752

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