40nm 12bit 60MHz 流水线式模数转换电路的设计

发布时间：2018-07-15 14:11

【摘要】：高性能模数转换电路是典型的数字电路与模拟电路相结合的产物,也是数字信号处理和单芯片(SoC)中不可或缺的接口单元,它能够将自然界中随处可见的、可感知的模拟信号转换成为易于传输处理的、抗干扰能力强的数字信号并输出给后级单元。本文给出了一款基于SMIC 40nm CMOS工艺的12bit 60MHz流水线式高性能模数转换器的整体设计方案。先是对几种常用的ADC结构进行了简单的原理介绍和性能对比,并详细介绍了Pipeline ADC的结构、原理及其性能优势。然后对Pipeline ADC中的两相不交叠时钟电路、采样保持电路、1.5bit每级级电路、运放电路、比较器电路、延迟校准电路、带隙基准电路等主要模块的工作原理、设计方案及前仿结果进行了详细的阐述。最后给出了各模块在40nm CMOS工艺下的版图设计及整体电路的后仿结果和各项参数。
[Abstract]:High performance A / D conversion circuit is the product of the combination of typical digital circuit and analog circuit. It is also an indispensable interface unit in digital signal processing and single chip (SoC). It can be seen everywhere in nature. The perceptible analog signal is converted into a digital signal which is easy to transmit and has strong anti-jamming ability and is output to the rear stage unit. In this paper, a design scheme of 12bit 60MHz pipelined high performance A / D converter based on SMIC 40nm CMOS process is presented. Firstly, the principle and performance of several common ADC structures are introduced and compared, and the structure, principle and performance advantages of pipeline ADC are introduced in detail. Then, the principle of the main modules in pipeline ADC, such as two-phase non-overlapping clock circuit, sampling and holding circuit, 1.5 bit per stage circuit, operational amplifier circuit, comparator circuit, delay calibration circuit, bandgap reference circuit, etc. The design scheme and pre-imitation result are described in detail. Finally, the layout design of each module in 40nm CMOS process and the post-simulation results and parameters of the whole circuit are given.
【学位授予单位】：兰州大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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