基于28nm工艺的低功耗触发器设计及优化
发布时间：2018-07-17 01:25
【摘要】：随着超大规模集成电路(VLSI)设计的快速发展,以及半导体工艺的不断更新,使得芯片在性能上有了很大的提升,越来越多的智能移动设备、智能穿戴设备涌现于市场。芯片集成度的不断提高,使其功耗和功耗密度问题也变得越来越突出。功耗的增加会引起芯片温度提高,严重影响电路的可靠性,对于移动智能设备,功耗的增加会降低其续航能力。低功耗设计已经成为VLSI设计的重要研究方向。一块芯片全部的能耗中,时钟网络的功耗占据了总功耗的30%-50%,而触发器是时钟网络电路中的主要部分,因此,低功耗触发器的设计对降低电路整体功耗有重要意义。通过分析CMOS电路的功耗来源,以及触发器的一些性能参数,并实际举例了典型的主从触发器,介绍了关于触发器的一些理论知识。在低功耗电路设计中,添加门控时钟电路是常用的一种设计方法,门控时钟技术的原理是利用使能信号控制电路在特定的时钟周期内让其闲置,并使得电路在需要工作的时候被激活工作,门控时钟技术的应用减少了电路的整体功耗。本文基于门控时钟电路设计了一种低功耗触发器,可以较好地降低由于信号翻转造成的动态功耗。在一定的时钟周期内,如果输入信号等于输出信号,即输入信号维持不变,那么门控时钟信号可控制触发器保持在闲置状态。最后基于28nm工艺进行了功能仿真,比较和分析了几种触发器的性能。分析可得,新设计的触发器在降低功耗上有较好的效果。其次,利用了逻辑努力方法对现有的几种主从触发器,以及本文设计的低功耗双门控触发器进行了优化。逻辑努力方法不依赖于寄生参数,使得电路设计在早期能通过简单的计算得到其最小延迟,有可靠的评估。用逻辑努力方法优化后的触发器在理论上速度到达最优,设计者可根据其特点应用在高速电路的关键路径中。
[Abstract]:With the rapid development of VLSI design and the continuous updating of semiconductor technology, the performance of chips has been greatly improved. More and more smart mobile devices have emerged in the market. With the continuous improvement of chip integration, the problem of power consumption and power density becomes more and more prominent. The increase of power consumption will increase the temperature of the chip and seriously affect the reliability of the circuit. For mobile intelligent devices, the increase of power consumption will reduce its ability to live. Low power design has become an important research direction in VLSI design. Among the total energy consumption of a chip, the power consumption of the clock network occupies 30-50% of the total power consumption, while the trigger is the main part of the clock network circuit. Therefore, the design of the low-power flip-flop is of great significance to reduce the overall power consumption of the circuit. By analyzing the power sources of CMOS circuits and some performance parameters of flip-flops, a typical master-slave flip-flop is illustrated, and some theoretical knowledge about flip-flop is introduced. In the design of low power circuit, adding gated clock circuit is a common design method. The principle of gating clock technology is to make use of enable signal control circuit to idle it in a specific clock period. The circuit is activated when it needs to work, and the application of gating clock technology reduces the overall power consumption of the circuit. In this paper, a low power flip-flop based on gated clock circuit is designed, which can reduce the dynamic power consumption caused by signal flipping. In a certain clock cycle, if the input signal is equal to the output signal, that is, the input signal remains unchanged, then the gated clock signal can control the trigger to remain idle. Finally, the function simulation based on 28nm process is carried out, and the performance of several flip-flops is compared and analyzed. The analysis shows that the new flip-flop has a good effect on reducing power consumption. Secondly, several existing master-slave flip-flop and low-power double-gated flip-flop are optimized by using logical effort method. The logical effort method does not depend on parasitic parameters, so that the circuit design can get its minimum delay by simple calculation in the early stage and have reliable evaluation. The logic effort method is used to optimize the speed of the flip-flop in theory, and the designer can apply it to the critical path of high speed circuit according to its characteristics.
【学位授予单位】：安徽大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47;TN783
本文编号：2128416
[Abstract]:With the rapid development of VLSI design and the continuous updating of semiconductor technology, the performance of chips has been greatly improved. More and more smart mobile devices have emerged in the market. With the continuous improvement of chip integration, the problem of power consumption and power density becomes more and more prominent. The increase of power consumption will increase the temperature of the chip and seriously affect the reliability of the circuit. For mobile intelligent devices, the increase of power consumption will reduce its ability to live. Low power design has become an important research direction in VLSI design. Among the total energy consumption of a chip, the power consumption of the clock network occupies 30-50% of the total power consumption, while the trigger is the main part of the clock network circuit. Therefore, the design of the low-power flip-flop is of great significance to reduce the overall power consumption of the circuit. By analyzing the power sources of CMOS circuits and some performance parameters of flip-flops, a typical master-slave flip-flop is illustrated, and some theoretical knowledge about flip-flop is introduced. In the design of low power circuit, adding gated clock circuit is a common design method. The principle of gating clock technology is to make use of enable signal control circuit to idle it in a specific clock period. The circuit is activated when it needs to work, and the application of gating clock technology reduces the overall power consumption of the circuit. In this paper, a low power flip-flop based on gated clock circuit is designed, which can reduce the dynamic power consumption caused by signal flipping. In a certain clock cycle, if the input signal is equal to the output signal, that is, the input signal remains unchanged, then the gated clock signal can control the trigger to remain idle. Finally, the function simulation based on 28nm process is carried out, and the performance of several flip-flops is compared and analyzed. The analysis shows that the new flip-flop has a good effect on reducing power consumption. Secondly, several existing master-slave flip-flop and low-power double-gated flip-flop are optimized by using logical effort method. The logical effort method does not depend on parasitic parameters, so that the circuit design can get its minimum delay by simple calculation in the early stage and have reliable evaluation. The logic effort method is used to optimize the speed of the flip-flop in theory, and the designer can apply it to the critical path of high speed circuit according to its characteristics.
【学位授予单位】：安徽大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47;TN783
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