基于AXI的SoC互联结构的设计与验证
发布时间：2018-07-17 20:17
【摘要】：随着集成电路的发展和半导体工艺的进步,基于IP核复用技术的片上系统(SoC)设计被越来越广泛的运用于各个领域。针对SoC中IP核的互连,传统的总线结构显现出传输带宽低、难以支持并行通信、地址空间有限等问题;IP核通信协议也常反映出难以实现低延时、高频率、低功耗和灵活性等缺点。本文研究设计了一种基于AXI协议的SoC matrix互联结构,一方面能够体现AXI协议的优点,在点对点传输时实现低延时、高效率和高吞吐率的特点,另一方面避免了总线结构的一些不足之处,实现N-M并行通信,最后并对设计进行功能验证。具体工作如下:1.分析AXI传输过程与结构特点,并结合系统并行通信的要求,设计出一种针对主设备的多数据缓存、针对目标从设备的共享地址多数据缓存的拓扑结构,实现IP核与互连架构模块的基于AXI协议的outstanding传输、乱序访问及N-M并行通信。2.带有仲裁配置寄存器,可通过相应的握手协议对该寄存器进行改写,使SoC在不同的应用场合下采用可定义的仲裁优先级实现更高效的通信。3.设计带AXI接口的SRAM控制器与AXI2APB Bridge,两者作为从设备挂载在AXI互连架构上,实现写操作中地址与数据无先后差别的传输,并对模块优化。4.搭建UVM验证平台对模块、部件进行功能验证,编写UVM中driver、monitor、sequencer、agent、reference model、scoreboard等组成部分,生成带约束的随机激励,并对结果进行自动检查,采用不同的testcase验证不同的功能点,并且验证结果正确。
[Abstract]:With the development of integrated circuits and semiconductor technology, the design of SoC based on IP core multiplexing technology is more and more widely used in various fields. For the interconnection of IP cores in SoC, the traditional bus architecture shows that the transmission bandwidth is low, it is difficult to support parallel communication, the address space is limited and so on, IP core communication protocols often reflect that it is difficult to achieve low delay and high frequency. The disadvantages of low power consumption and flexibility. In this paper, a matrix interconnection architecture based on AXI-based protocol is designed. On the one hand, it can embody the advantages of AXIprotocol and realize the characteristics of low delay, high efficiency and high throughput in point-to-point transmission. On the other hand, it avoids some shortcomings of bus architecture, realizes N-M parallel communication, and verifies the function of the design. The work is as follows: 1. This paper analyzes the characteristics of AXI transmission process and structure, and designs a topology of multi-data cache for main equipment and shared address multi-data cache for target slave device, combined with the requirement of system parallel communication. The implementation of IP core and interconnection architecture module based on AXI-based outstanding transmission, out-of-order access and N-M parallel communication. 2. With the arbitration configuration register, the register can be rewritten by the corresponding handshake protocol, so that SoC can use the defined arbitration priority to achieve more efficient communication. The SRAM controller with AXI interface and the AXI2APB bridge are designed, which are mounted on the AXI interconnection architecture as slave devices to realize the transmission of the address and data in the write operation, and optimize the module. 4. Building a verification platform for modules and components to verify the function of modules and components, writing components such as driver monitor and sequence reference model scoreboard, generating random excitation with constraints, and automatically checking the results, and using different testcase to verify different function points. And verify the results are correct.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47
本文编号：2130820
[Abstract]:With the development of integrated circuits and semiconductor technology, the design of SoC based on IP core multiplexing technology is more and more widely used in various fields. For the interconnection of IP cores in SoC, the traditional bus architecture shows that the transmission bandwidth is low, it is difficult to support parallel communication, the address space is limited and so on, IP core communication protocols often reflect that it is difficult to achieve low delay and high frequency. The disadvantages of low power consumption and flexibility. In this paper, a matrix interconnection architecture based on AXI-based protocol is designed. On the one hand, it can embody the advantages of AXIprotocol and realize the characteristics of low delay, high efficiency and high throughput in point-to-point transmission. On the other hand, it avoids some shortcomings of bus architecture, realizes N-M parallel communication, and verifies the function of the design. The work is as follows: 1. This paper analyzes the characteristics of AXI transmission process and structure, and designs a topology of multi-data cache for main equipment and shared address multi-data cache for target slave device, combined with the requirement of system parallel communication. The implementation of IP core and interconnection architecture module based on AXI-based outstanding transmission, out-of-order access and N-M parallel communication. 2. With the arbitration configuration register, the register can be rewritten by the corresponding handshake protocol, so that SoC can use the defined arbitration priority to achieve more efficient communication. The SRAM controller with AXI interface and the AXI2APB bridge are designed, which are mounted on the AXI interconnection architecture as slave devices to realize the transmission of the address and data in the write operation, and optimize the module. 4. Building a verification platform for modules and components to verify the function of modules and components, writing components such as driver monitor and sequence reference model scoreboard, generating random excitation with constraints, and automatically checking the results, and using different testcase to verify different function points. And verify the results are correct.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47
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