CMOS电荷泵锁相环的分析与设计
发布时间：2018-07-20 12:14
【摘要】： 在研究大量资料的基础之上,先对锁相系统的基本工作原理进行了分析,以传统模拟锁相环的结构为基础,分析了锁相环的数学模型,并以此为出发点对锁相环的跟踪性能、捕获性能、及稳定性等各种性能进行了分析。由于本设计采用的是电荷泵锁相环的形式,它的结构与传统的锁相环有所不同,因此论文从系统设计角度出发对电荷泵锁相环的工作原理、数学模型以及基本性能也进行了比较详细的分析,进一步地研究了环路性能、环路参数。然后对电荷泵锁相环的基本模块——鉴频鉴相器、电荷泵以及压控振荡器的常用电路进行了结构分析和性能比较。 本文设计了一个用于USB 2.0 PHY时钟恢复电路的锁相环频率综合器,论文主要阐述了这个电路系统的设计方法。环路中的鉴频鉴相器采用了双边沿触发的电路结构,有效地减小了传统鉴频鉴相器中的死区。电荷泵结构也作了一定的改进,采用了消除过冲现象的电荷泵电路,减小了非理想因素。本文对锁相环核心模块压控振荡器进行了深入研究与设计,实现了一个高线性度差分结构的压控振荡器。分频器采用单相时钟TSPC逻辑实现。 电路设计和HSPICE仿真基于UMC0.25umCMOS工艺,从锁相环的仿真结果可知,我们的理论研究结果和实验结果相符。
[Abstract]:Based on the study of a large amount of data, the basic working principle of the phase-locked system is analyzed. Based on the structure of the traditional simulated PLL, the mathematical model of PLL is analyzed, and the tracking performance of PLL is taken as a starting point. The performance of capture and stability are analyzed. Because this design adopts the form of the charge pump phase-locked loop, its structure is different from the traditional phase-locked loop, so this paper starts from the system design angle to the charge pump phase-locked loop's working principle. The mathematical model and basic performance are also analyzed in detail, and the loop performance and loop parameters are further studied. Then, the structure analysis and performance comparison of the basic modules of the charge pump phase-locked loop frequency discriminator, charge pump and voltage-controlled oscillator are carried out. A phase-locked loop frequency synthesizer for USB 2.0 PHY clock recovery circuit is designed in this paper. The circuit structure of double edge trigger is adopted in the phase discriminator of the loop, which effectively reduces the dead zone in the traditional phase discriminator. The structure of the charge pump is improved to a certain extent, and the charge pump circuit is used to eliminate overshoot, which reduces the non-ideal factor. In this paper, the voltage controlled oscillator (VCO), which is the core module of PLL, is deeply studied and designed, and a VCO with high linearity difference structure is realized. The divider is implemented by single phase clock TSPC logic. The circuit design and HSPICE simulation are based on UMC 0.25 um CMOS process. From the simulation results of the PLL, we can see that our theoretical results are in agreement with the experimental results.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2007
【分类号】：TN911.8
本文编号：2133481
[Abstract]:Based on the study of a large amount of data, the basic working principle of the phase-locked system is analyzed. Based on the structure of the traditional simulated PLL, the mathematical model of PLL is analyzed, and the tracking performance of PLL is taken as a starting point. The performance of capture and stability are analyzed. Because this design adopts the form of the charge pump phase-locked loop, its structure is different from the traditional phase-locked loop, so this paper starts from the system design angle to the charge pump phase-locked loop's working principle. The mathematical model and basic performance are also analyzed in detail, and the loop performance and loop parameters are further studied. Then, the structure analysis and performance comparison of the basic modules of the charge pump phase-locked loop frequency discriminator, charge pump and voltage-controlled oscillator are carried out. A phase-locked loop frequency synthesizer for USB 2.0 PHY clock recovery circuit is designed in this paper. The circuit structure of double edge trigger is adopted in the phase discriminator of the loop, which effectively reduces the dead zone in the traditional phase discriminator. The structure of the charge pump is improved to a certain extent, and the charge pump circuit is used to eliminate overshoot, which reduces the non-ideal factor. In this paper, the voltage controlled oscillator (VCO), which is the core module of PLL, is deeply studied and designed, and a VCO with high linearity difference structure is realized. The divider is implemented by single phase clock TSPC logic. The circuit design and HSPICE simulation are based on UMC 0.25 um CMOS process. From the simulation results of the PLL, we can see that our theoretical results are in agreement with the experimental results.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2007
【分类号】：TN911.8
【参考文献】
相关期刊论文 前3条
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