具有倒装及堆叠技术的DrMOS封装工艺研究

发布时间：2018-07-23 20:02

【摘要】：功率芯片组封装必须妥善解决散热问题,堆叠封装尤其需要重视,因为堆叠使散热面积缩小,热积聚现象将更加明显,有关这一类问题的研究报道很多,但是功率器件堆叠封装的产品并不多见,因此,如何在现有技术体系中通过结构设计、流程重整和关键工艺改良解决上述问题,是这一类新产品开发过程中必须面对的课题。本项目研究围绕一种新型功率器件模组产品QFN3.5x5的堆叠封装技术开发展开,该模组包含两个MOSFET功率器件芯片和一个控制电路IC芯片,研究的目标是形成散热结构合理的堆叠封装架构,以便在体积显著缩小的同时,维持良好热稳定性,重点是开发堆叠封装成套工艺,完成模组封装和关键特性测试。为此,首先通过论证确立了堆叠封装的整体结构设计,然后通过Abaqus软件进行仿真分析,优化封装结构;接着,针对该优化的封装结构,提出封装工艺流程设计方案,据此整合已有单元工艺,优化关键单项技术,形成模块封装成套工艺,完成模组批量试生产及热应力特性测试。所提出的整体封装架构是在主体的铜引线框架双侧表面分别贴装一块MOSFET功率芯片,然后在上管芯之上堆叠控制电路IC芯片,再通过引线键合互连并塑封。采用导热能力突出的铜片作为主体结构就是为了更好地解决功率芯片的热量导出问题。封装工艺全流程可以分为两个部分,即晶圆级预处理工艺模块和组装键合工艺模块。晶圆级预处理工艺包括以下主要工序:晶圆正面化学镀NiAu--植高铅锡球--回流焊--清洗--晶圆正面用环氧树脂塑封--正面减薄露出铅锡电极--晶圆背面减薄--蒸镀Ti Ni Ag金属层。组装键合工艺模块流程如下:用高铅焊锡料倒装粘结下管芯片--用高铅焊锡料粘结上管芯片和铜片--清洗--堆叠IC芯片到铜片上--固化绝缘胶--引线键合--塑封--后道切割等。围绕如何打通上述封装工艺全流程,实现良好封装效果,在现有的DrMOS封装工艺线基础上,重点研究了高铅锡球植球工艺、晶圆正面环氧树脂塑封工艺、下管芯片高铅焊锡料倒装粘结工艺、上管芯片高铅焊锡料粘结铜片工艺、以及清洗工艺等单项技术。其中,氋铅锡球植球借用成熟的丝网印刷技术,根据本产品的特点开发了专用的丝网以符合产品的要求。圆晶减薄有助于快速散热,但是减薄操作容易发生碎裂或其他破损,影响成品率,晶圆正面的环氧树脂作为一种支撑,可以在芯片很薄的情况下保护其不易受损,通过系统优化,使该工艺达到可以工业化生产的程度也为将来芯片进一步减薄创造了条件。高铅焊锡料倒装粘结下管芯容易出现点胶不稳定的问题,通过对点胶过程的细致分析,根据点胶头的孔径选择合理的点胶高度有助于稳定工艺效果,较大的孔径对稳定的点胶非常重要。高铅焊锡料粘结上管芯片设计了框架卡槽来对铜片进行定位,防止铜片旋转,提高了产品的良品率。清洗工艺研究了市面上比较流行的清洗药水和清洗参数对产品后续引线键合的影响,指明了优化的参数和药水型号。本文根据上述结构设计和工艺的研究,将优化方案整合到整体的工艺流程里,确定了这种新型驱动功率器件模组工艺的制造流程。通过工艺参数优化提升了单项工艺稳定可重复性,然后采用如上所述的工艺制造了一种新型的驱动电源管理器件模组(DrMOS)模型采用专业的电子热分析有限元软件Flothermal,研究了高密度封装DrMOS模块在PCB板上集成典型设计的温度分布,提出了新型DrMOS模块应用设计的一些建议。对封装产品取样测试表明,样品在典型功率负载下的温度分布和热应力变形均在设计预期和应用允许的范围之内,功率效率显著提升,这充分说明利用多种先进封装技术完成的本项新产品,在体积显著降低的同时性能得到提升,开发获得成功。
[Abstract]:The power chip package package must properly solve the heat dissipation problem, and the stack package should be paid more attention, because the stack makes the heat dissipation area narrow, the heat accumulation phenomenon will be more obvious. There are many reports about this kind of problem. But the products of power device stacking package are not common. Therefore, how to design the structure in the existing technology system, Process reforming and key process improvement to solve the above problems is a subject that must be faced in the development of this kind of new product. This project is developed around a new type of power device module product QFN3.5x5 stacked package technology, which includes two MOSFET power devices core and a control circuit IC chip. It is a stacked package structure that forms a reasonable heat dissipation structure so as to maintain good thermal stability while reducing the volume significantly. The focus is to develop a stack package process, complete module package and key characteristic test. For this reason, the whole structure design of stacked package is established by demonstration, and then the simulation is carried out through Abaqus software. Then, the packaging structure is optimized. Then, in view of the optimized package structure, the package process flow design scheme is put forward to integrate the existing unit process, optimize the key single item technology, form the package package process, complete the module batch production and thermal stress characteristics test. The overall package architecture is the copper lead frame of the main body. A MOSFET power chip is mounted on both sides of the surface, then the control circuit IC chip is stacked above the upper tube core, and then the lead bonding is used to interconnect and seal. The copper sheet with the outstanding thermal conductivity is used as the main structure to better solve the heat export problem of the power chip. The whole process of the packaging process can be divided into two parts. Wafer level pre treatment process module and assembly bonding process module. The wafer level preprocessing technology includes the following main processes: wafer front chemical plating NiAu-- high lead tin balls - reflow soldering - Cleaning - epoxy resin sealing on the front of the wafer -- the front thin exposed lead tin electrode - the back of wafer surface thinning - Ti Ni Ag metal layer. Assembly bonding process The module flow is as follows: using high lead solder paste to bond the pipe chip - using high lead solder to bond tube chip and copper chip - Cleaning - stacked IC chip to copper chip - curing insulating adhesive - lead bonding - plastic seal - back cut, etc. On the basis of the art line, it focuses on the technology of high lead tin ball planting, the plastic sealing process of the epoxy resin in the front of the wafer, the bonding process of the high lead solder material in the pipe chip, the technology of the bonding copper sheet of the high lead solder material on the pipe chip, and the cleaning technology. A special screen is developed to meet the requirements of the product. The thinning of the circular crystal helps to heat the heat quickly, but the thinning operation is easily broken or other breakage, affecting the yield. The epoxy resin on the front of the wafer can be used as a support and can not be easily damaged under the thin chip of the chip. The process can be optimized by system optimization. The degree of industrial production also creates conditions for further thinning of chips in the future. The high lead solder paste chip designed the frame card slot to locate the copper sheet, prevent the copper sheet from rotated and improve the product's good product rate. The cleaning process has studied the influence of the popular cleaning water and cleaning parameters on the following lead bonding of the product, pointing out the optimized parameters and the model of the medicine water. This paper is based on this paper. In the study of the structure design and process, the optimization scheme is integrated into the whole process flow, and the manufacturing process of the new driving power device module is determined. The stability and repeatability of the single process are improved by optimizing the process parameters. Then a new type of power management device is made by the technology described above. The model module (DrMOS) model uses the specialized electronic thermal analysis finite element software Flothermal to study the temperature distribution of the typical design of the high density package DrMOS module on the PCB board, and puts forward some suggestions for the application design of the new DrMOS module. The force deformation is within the range of design expectation and application, and the power efficiency is greatly improved. This fully illustrates the new product completed by various advanced packaging technology. The performance is improved while the volume is significantly reduced, and the development is successful.
【学位授予单位】：上海交通大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN405

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