TIADC系统时钟失配误差校正算法研究
发布时间：2018-08-04 14:45
【摘要】：现代电子设备对于采样速率的需求越来越高,时间交替并行采样模数转换器(Time-Interleaved ADC, TIADC)是一种有效的方法,它能够保证单通道ADC的采样精度,同时大幅提高系统采样率。但是TIADC系统中存在的增益误差(Gain error)、偏置误差(offset error)和时钟偏斜误差(time skew error)严重影响着系统的性能,因此,TIADC系统通道失配误差的校正成为了研究热点。文章给出了一种基于完美重构的误差校正算法以及算法的全并行实现结构。通过查阅大量的文献资料,对TIADC系统的基本原理和误差进行了研究和分析。误差校正算法的关键在于校正滤波器的设计,采用加权最小二乘法对其进行改善,并且在实现上进行改进,使得该算法在保证性能的基础上,得以适用于更高的频率范围。在校正算法的研究上,本文采用基于正弦拟合的通道失配估算方法对误差估计算法进行了研究,给出了基于完美重构的校正滤波器的设计,在最小二乘法的基础上,采用了加权最小二乘法对校正滤波器进行改进,使得系统性能得到大幅改善。在校正电路的研究上,采用全并行结构,利用串并转换实现高速数据的降速,再利用滤波器的多相分解技术构建滤波器阵列对时钟失配误差进行实时校正,提高了电路的吞吐量。最后,基于FPGA实现了四通道12bit 800MSPS的TIADC系统。所设计的校正电路实现简单,性能良好。Modelsim和MATLAB平台上的仿真与分析结果均表明,校正后TIADC系统的性能和校正前相比得到了大幅提高,并满足设计要求。
[Abstract]:The demand of sampling rate for modern electronic equipment is increasing. Time-Interleaved ADC, TIADC) is an effective method, which can guarantee the sampling accuracy of single channel ADC and greatly improve the sampling rate of the system. However, the gain error, (Gain error), bias error (offset error) and clock skew error (time skew error) exist in TIADC system seriously affect the performance of the system, so the correction of channel mismatch error in TIADC system has become a hot research topic. In this paper, an error correction algorithm based on perfect reconstruction and its full parallel implementation structure are presented. The basic principle and error of TIADC system are studied and analyzed by consulting a lot of documents. The key of the error correction algorithm is the design of the correction filter, which is improved by the weighted least square method and improved in the implementation, so that the algorithm can be applied to a higher frequency range on the basis of ensuring the performance. In this paper, the error estimation algorithm based on sinusoidal fitting is studied, and the design of correction filter based on perfect reconstruction is given. The weighted least square method is used to improve the correction filter, and the system performance is greatly improved. In the research of correction circuit, the parallel structure is adopted to realize the speed reduction of high speed data by using series-parallel conversion, and the filter array is constructed to correct the clock mismatch error in real time by using the polyphase decomposition technology of the filter. The throughput of the circuit is improved. Finally, a four-channel 12bit 800MSPS TIADC system is implemented based on FPGA. The results of simulation and analysis on the platform of .Modelsim and MATLAB show that the performance of the corrected TIADC system has been greatly improved compared with that of the pre-calibration system, and meets the design requirements.
【学位授予单位】：北京化工大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN713
本文编号：2164205
[Abstract]:The demand of sampling rate for modern electronic equipment is increasing. Time-Interleaved ADC, TIADC) is an effective method, which can guarantee the sampling accuracy of single channel ADC and greatly improve the sampling rate of the system. However, the gain error, (Gain error), bias error (offset error) and clock skew error (time skew error) exist in TIADC system seriously affect the performance of the system, so the correction of channel mismatch error in TIADC system has become a hot research topic. In this paper, an error correction algorithm based on perfect reconstruction and its full parallel implementation structure are presented. The basic principle and error of TIADC system are studied and analyzed by consulting a lot of documents. The key of the error correction algorithm is the design of the correction filter, which is improved by the weighted least square method and improved in the implementation, so that the algorithm can be applied to a higher frequency range on the basis of ensuring the performance. In this paper, the error estimation algorithm based on sinusoidal fitting is studied, and the design of correction filter based on perfect reconstruction is given. The weighted least square method is used to improve the correction filter, and the system performance is greatly improved. In the research of correction circuit, the parallel structure is adopted to realize the speed reduction of high speed data by using series-parallel conversion, and the filter array is constructed to correct the clock mismatch error in real time by using the polyphase decomposition technology of the filter. The throughput of the circuit is improved. Finally, a four-channel 12bit 800MSPS TIADC system is implemented based on FPGA. The results of simulation and analysis on the platform of .Modelsim and MATLAB show that the performance of the corrected TIADC system has been greatly improved compared with that of the pre-calibration system, and meets the design requirements.
【学位授予单位】：北京化工大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN713
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