基于0.6μm CMOS工艺的ESD保护器件研究

发布时间：2018-08-04 19:55

【摘要】：静电放电(Electrostatic Discharge,ESD)是日常生活中的常见现象,它与半导体可靠性问题联系紧密。在集成电路产业中,ESD失效在总失效模式中占据了很大比例,造成了大量的经济损失,随着工艺线宽的不断缩小,半导体制造技术的不断创新,ESD问题将会更加严重,因此研究ESD保护对于提高半导体可靠性非常必要。本文首先介绍了ESD保护的基本理论,阐述了人体模型(HBM)、机器模型(MM)、组件充电模型(CDM)三种ESD放电物理模型以及TLP与电子抢的测试方法。其次介绍了CMOS工艺下常用的保护器件,包括二极管特性曲线分析,反向雪崩击穿电压的公式推导;电阻在用作ESD保护时的具体应用范例;MOSFET在两种不同导电模式下的优缺点;SCR降低触发电压与维持电压的方法与原理。随后基于0.6μm CMOS工艺,对常用ESD保护器件流片实现、TLP测试分析总结出它们在该工艺下的ESD性能表现。重点针对SCR类保护器件,通过结构优化,尺寸调节等措施不断降低触发电压,提高维持电压;并设计出一种具有低触发电压的新型GCSCR结构,当ESD脉冲来临时,通过内嵌RC网络来触发开启NMOS,开启后的NMOS衬底电流流经衬底电阻开启NPN结构,进而开启SCR。该结构先通过仿真观察其电势分布与电流路径验证了它的工作原理,流片实现后也表现出不错的ESD性能。最后介绍了用于板级电路ESD保护的器件TVS及其阵列,介绍了它的应用场合以及特性,根据需求指标,设计出了三种用于1.8V低压电路的ESD保护器件。它们都是基于外部辅助电路注入电流从而正向偏置寄生BJT发射结开启SCR,实验结果表明,当改变辅助触发电路的堆叠二极管或NMOS的个数和宽度时可以设计出具有不同触发电压的SCR结构,该结构具有很大的设计灵活性。
[Abstract]:Electrostatic discharge (ESD) is a common phenomenon in daily life, which is closely related to the reliability of semiconductors. In the integrated circuit industry, ESD failure accounts for a large proportion of the total failure mode, resulting in a large number of economic losses. With the continuous reduction of process line width, the continuous innovation of semiconductor manufacturing technology will become more serious. Therefore, it is necessary to study ESD protection for improving semiconductor reliability. In this paper, the basic theory of ESD protection is introduced, and three kinds of ESD discharge physical models of human body model, (HBM), machine model, (MM), module charging model, (CDM), and the test methods of TLP and electron gun are described. Secondly, the common protective devices in CMOS process are introduced, including the analysis of diode characteristic curve and the derivation of the formula of reverse avalanche breakdown voltage. The application of resistance in ESD protection is illustrated by the method and principle of reducing trigger voltage and maintaining voltage in two different conduction modes. Then, based on 0.6 渭 m CMOS process, the ESD performances of ESD protection devices are analyzed and analyzed. Aiming at the SCR protection devices, the trigger voltage is reduced and the maintenance voltage is increased by optimizing the structure and adjusting the dimension, and a new type of GCSCR structure with low trigger voltage is designed. When the ESD pulse comes, a new type of GCSCR structure with low trigger voltage is designed. Through the embedded RC network to trigger the opening of NMOSs, the NMOS substrate current flows through the substrate resistor to open the NPN structure, and then open the NPN structure. The working principle of the structure is verified by observing its potential distribution and current path through simulation, and the ESD performance is also shown after the realization of the wafer. Finally, the device TVS and its array used for ESD protection of board level circuits are introduced. Its application and characteristics are introduced. According to the requirements, three kinds of ESD protection devices for 1.8V low-voltage circuits are designed. Both of them are based on the external auxiliary circuit injection current and thus the forward bias parasitic BJT emission junction is opened. The experimental results show that, When the number and width of stacked diodes or NMOS of the auxiliary trigger circuit are changed, the SCR structure with different trigger voltages can be designed, which has great flexibility in design.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN40

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