基于FPGA的串行RapidIO接口的设计与实现

发布时间：2018-08-05 15:18

【摘要】：随着嵌入式处理器性能的不断提升,传统的并行总线互连方案已经满足不了其日益增长的带宽需求。取而代之的Rapid IO互连技术具有速率高、成本低、引脚数少等优点,可以满足高性能嵌入式系统的广泛需求。作为当前嵌入式领域内唯一得到授权的国际标准,Rapid IO也是未来解决高性能嵌入式互连的最佳方案。目前,世界上几乎所有的嵌入式主流厂商都已经支持Rapid IO互连技术,并源源不断地推出各种基于Rapid IO规范的产品,涵盖了各种开发工具、嵌入式系统、IP、软件、测试设备以及半导体产品等。本论文对Rapid IO互连协议进行了研究,并参考相关产品的技术文档设计实现了一款基于RapidIO协议的串行互连接口。该接口实现了数据包的组包和解包、数据包的有序收发、初始化操作以及接收方控制的流量控制等基本功能。论文中首先介绍了有关Rapid IO互连技术的研究背景和国内外发展现状,然后分析了Rapid IO互连协议的分层体系结构、典型操作流程、常用操作类型、各种数据单元的格式和流量控制等内容,最后根据需要提取了协议中串行链路部分的基本功能,并提出串行Rapid IO接口电路的总体设计方案。基于Top-Down的设计思路和模块化的设计方法,使用Verilog硬件描述语言设计实现了组包逻辑、解包逻辑、逻辑层调度逻辑、初始化状态机、发送通道、接收通道以及重传恢复状态机等主要功能模块;为了减小设计的难度,高速串行收发电路采用Xilinx公司的FPGA中的Rocket IO硬核IP实现。此外,本文还分析了电路的时钟域划分和时钟分配,对异步信号的交互进行了跨时钟域处理。最后基于Modelsim软件搭建了仿真验证平台,对所设计的串行Rapid IO接口电路分别进行了模块级仿真和整体仿真。FPGA下板测试结果显示,本论文中所设计的串行Rapid IO接口电路功能正确。
[Abstract]:With the improvement of embedded processor performance, the traditional parallel bus interconnection scheme can not meet its growing bandwidth requirements. Instead of Rapid IO interconnection technology, it has the advantages of high speed, low cost and fewer pins, so it can meet the needs of high performance embedded systems. As the only authorized international standard in embedded field, Rapid IO is the best way to solve high performance embedded interconnection in the future. At present, almost all the mainstream embedded manufacturers in the world have supported the Rapid IO interconnection technology, and have continuously introduced a variety of products based on the Rapid IO specification, covering all kinds of development tools, embedded systems, IPOs, software, etc. Test equipment and semiconductor products. In this paper, the Rapid IO interconnection protocol is studied, and a serial interconnect interface based on RapidIO protocol is designed and implemented by referring to the technical documents of related products. The interface realizes the basic functions of packet formation and unpacking, packet sending and receiving orderly, initialization operation and flow control controlled by receiver, etc. This paper first introduces the research background of Rapid IO interconnection technology and its development status at home and abroad, then analyzes the layered architecture, typical operation flow, common operation types of Rapid IO interconnection protocol. Finally, the basic functions of serial link part in the protocol are extracted according to the need, and the overall design scheme of serial Rapid IO interface circuit is put forward. Based on the design idea and modular design method of Top-Down, this paper uses Verilog hardware description language to design and implement packet grouping logic, unpacking logic, logic layer scheduling logic, initialization state machine, sending channel, and so on. In order to reduce the difficulty of design, the high-speed serial transceiver is implemented by Rocket IO hard core IP in FPGA of Xilinx Company. In addition, the clock domain division and clock allocation of the circuit are analyzed, and the cross-clock domain processing of asynchronous signal interaction is carried out. Finally, the simulation platform is built based on Modelsim software. The module level simulation and the whole simulation. The test results show that the serial Rapid IO interface circuit designed in this paper has the correct function.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP334.7;TN791

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