高速链路均衡电路的能效优化及分数间隔FFE设计
发布时间：2018-08-07 18:03
【摘要】：随着云计算、大数据、物联网等技术的快速发展,人们对通信系统的带宽要求日益增加,但同时又希望将功耗控制在合理的范围之内。因此,如何以低成本可靠地传输高速数据受到越来越多的关注。本文研究了高速链路均衡电路的能效优化,对在给定速率、信道、链路指标等条件下寻找出能效最优均衡结构的方法进行了研究。利用统计分析技术,得到符合链路约束条件的多种均衡结构组合；利用能效建模技术,可以得到各均衡器在不同速率下的能效,通过两种技术结合便可从满足链路约束条件的众多均衡结构组合中筛选出能效优化方案,具有实用性和准确度。本文还研究了分数间隔前馈均衡器的设计与实现,采用0.18μmCMOS工艺设计了6.25Gb/s+的4抽头,抽头间隔为1/3符号周期的连续时间前馈均衡器。有源延时线采用源极电容衰减结构拓展带宽,并采用电容和电阻校准技术减轻工艺角变化对电路性能的影响,输出缓冲级借助片上电感提供增益和扩展带宽。该均衡器版图面积为0.49mmm2(含焊盘),已经流片。后仿真结果表明,对于经过24英寸PCB信道的6.25Gb/s伪随机序列信号和经过18英寸PCB信道的10Gb/s伪随机序列信号,该均衡器可以在码间干扰非常严重的情况下,有效改善眼图。在通信系统飞速发展的今天,本文研究的均衡电路能效优化流程有助于解决高速链路面临的速度和功耗矛盾,所设计和实现的前馈均衡器对于高速接收机的实现具有重要意义。
[Abstract]:With the rapid development of cloud computing, big data, Internet of things and other technologies, the bandwidth requirements of communication systems are increasing day by day, but at the same time, we hope to control the power consumption within a reasonable range. Therefore, how to transmit high-speed data with low cost and reliability has attracted more and more attention. In this paper, the energy efficiency optimization of high speed link equalization circuit is studied, and the method of finding the optimal equalization structure of energy efficiency under the given rate, channel, link index and so on is studied. By using the statistical analysis technique, we can obtain a variety of equalization structures that meet the link constraint conditions, and by using the energy efficiency modeling technology, we can get the energy efficiency of each equalizer at different rates. The energy efficiency optimization scheme can be selected from the combination of many equalization structures which satisfy the link constraint condition by combining the two techniques. It has practicability and accuracy. In this paper, the design and implementation of fractional interval feedforward equalizer are also studied. The 4-tap of 6.25Gb/s is designed by using 0.18 渭 mCMOS process, and the continuous time feedforward equalizer with 1 / 3 symbol period is designed. The active delay line uses the source capacitor attenuation structure to expand the bandwidth, and adopts the capacitance and resistance calibration technology to reduce the influence of the process angle change on the circuit performance. The output buffer stage provides the gain and the expanded bandwidth with the help of on-chip inductance. The equalizer layout area is 0.49mmm2 (including solder pad) and has been flattened. The post-simulation results show that the equalizer can effectively improve the eye diagram of 6.25Gb/s pseudorandom sequence signals over 24-inch PCB channel and 10Gb/s pseudorandom sequence signals over 18-inch PCB channel under very serious inter-symbol interference. With the rapid development of communication system, the energy efficiency optimization flow of equalization circuit studied in this paper is helpful to solve the contradiction between speed and power consumption in high speed link. The feedforward equalizer designed and implemented is of great significance to the realization of high speed receiver.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN715
本文编号：2170882
[Abstract]:With the rapid development of cloud computing, big data, Internet of things and other technologies, the bandwidth requirements of communication systems are increasing day by day, but at the same time, we hope to control the power consumption within a reasonable range. Therefore, how to transmit high-speed data with low cost and reliability has attracted more and more attention. In this paper, the energy efficiency optimization of high speed link equalization circuit is studied, and the method of finding the optimal equalization structure of energy efficiency under the given rate, channel, link index and so on is studied. By using the statistical analysis technique, we can obtain a variety of equalization structures that meet the link constraint conditions, and by using the energy efficiency modeling technology, we can get the energy efficiency of each equalizer at different rates. The energy efficiency optimization scheme can be selected from the combination of many equalization structures which satisfy the link constraint condition by combining the two techniques. It has practicability and accuracy. In this paper, the design and implementation of fractional interval feedforward equalizer are also studied. The 4-tap of 6.25Gb/s is designed by using 0.18 渭 mCMOS process, and the continuous time feedforward equalizer with 1 / 3 symbol period is designed. The active delay line uses the source capacitor attenuation structure to expand the bandwidth, and adopts the capacitance and resistance calibration technology to reduce the influence of the process angle change on the circuit performance. The output buffer stage provides the gain and the expanded bandwidth with the help of on-chip inductance. The equalizer layout area is 0.49mmm2 (including solder pad) and has been flattened. The post-simulation results show that the equalizer can effectively improve the eye diagram of 6.25Gb/s pseudorandom sequence signals over 24-inch PCB channel and 10Gb/s pseudorandom sequence signals over 18-inch PCB channel under very serious inter-symbol interference. With the rapid development of communication system, the energy efficiency optimization flow of equalization circuit studied in this paper is helpful to solve the contradiction between speed and power consumption in high speed link. The feedforward equalizer designed and implemented is of great significance to the realization of high speed receiver.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN715
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1 李峰灯;高速链路均衡电路的能效优化及分数间隔FFE设计[D];东南大学;2016年
，本文编号：2170882
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