快速锁定的高速低抖动时钟发生器的研究与设计
发布时间：2018-08-09 14:31
【摘要】：随着经济社会的日新月异,移动互联网的逐渐普及,消费类电子产品越来越受到大众的喜爱。作为消费类电子产品中必不可少的时钟产生电路,伴随着数字信号处理技术的高速发展,通信设备、电子产品的工作频率的不断提高,对时钟发生器速度与精度的要求也越来越高,因此对高速低抖动时钟发生器的研究具有重要意义。首先,本文阐述了电荷泵锁相环的基本原理,以及锁相环在锁定之前的响应行为和锁定状态下的线性模型。深入分析了电荷泵锁相环的相位噪声和非理想效应,并推导了模数转换器对系统时钟抖动的要求,据此提出了本设计中的时钟发生器的性能指标并选取了二类三阶电荷泵锁相环作为本设计中的时钟发生器的主体电路。接着,本文介绍了电荷泵锁相环各单元模块的工作原理和主要电路结构。结合1.2V电源电压的55nm标准CMOS工艺,在对该时钟发生器性能指标综合分析的基础上完成了各单元模块的设计,并提出了利用MOSFET反向导通的原理,在没有增加电路复杂度的前提下实现了时钟发生器的快速锁定。最后,利用CADENCE、HSPICE和SPECTRE等模拟集成电路设计工具,对各单元模块和整个环路系统进行了仿真验证,并完成了整个环路系统的版图设计。仿真结果表明:在温度为25℃,TT工艺角下,时钟发生器输出1.62GHz方波信号时的时钟抖动为2.27ps,锁定时间为3.3μs。在1.2V电源电压下,系统的总功耗为4.28mW。最终版图面积为1109*1054μm2。
[Abstract]:With the rapid development of economy and society and the popularity of mobile internet, consumer electronic products are more and more popular. As an indispensable clock generation circuit in consumer electronic products, with the rapid development of digital signal processing technology, communication equipment, electronic products working frequency continues to improve, The speed and precision of clock generator are required more and more, so the research of high speed and low jitter clock generator is of great significance. Firstly, the basic principle of charge pump phase-locked loop (CPPLL), the response behavior of PLL before locking and the linear model of PLL under locking state are described. The phase noise and non-ideal effect of the charge pump phase-locked loop (CPPLL) are analyzed in depth, and the requirements of A / D converter for system clock jitter are derived. Based on this, the performance index of the clock generator in this design is put forward, and the second kind of third order charge pump phase-locked loop is selected as the main circuit of the clock generator in this design. Then, this paper introduces the working principle and main circuit structure of each unit module of the charge pump phase-locked loop. Combined with 55nm standard CMOS process with 1.2V power supply voltage, the design of each unit module is completed on the basis of synthetically analyzing the performance index of the clock generator, and the principle of using MOSFET reverse conduction is put forward. The fast locking of the clock generator is realized without increasing the complexity of the circuit. Finally, the simulation of each unit module and the whole loop system is carried out by using the analog integrated circuit design tools such as CADENCEN HSpice and SPECTRE, and the layout design of the whole loop system is completed. The simulation results show that the clock jitter is 2.27 psand the locking time is 3.3 渭 s when the clock generator outputs the 1.62GHz square wave signal at 25 鈩，
本文编号：2174381
[Abstract]:With the rapid development of economy and society and the popularity of mobile internet, consumer electronic products are more and more popular. As an indispensable clock generation circuit in consumer electronic products, with the rapid development of digital signal processing technology, communication equipment, electronic products working frequency continues to improve, The speed and precision of clock generator are required more and more, so the research of high speed and low jitter clock generator is of great significance. Firstly, the basic principle of charge pump phase-locked loop (CPPLL), the response behavior of PLL before locking and the linear model of PLL under locking state are described. The phase noise and non-ideal effect of the charge pump phase-locked loop (CPPLL) are analyzed in depth, and the requirements of A / D converter for system clock jitter are derived. Based on this, the performance index of the clock generator in this design is put forward, and the second kind of third order charge pump phase-locked loop is selected as the main circuit of the clock generator in this design. Then, this paper introduces the working principle and main circuit structure of each unit module of the charge pump phase-locked loop. Combined with 55nm standard CMOS process with 1.2V power supply voltage, the design of each unit module is completed on the basis of synthetically analyzing the performance index of the clock generator, and the principle of using MOSFET reverse conduction is put forward. The fast locking of the clock generator is realized without increasing the complexity of the circuit. Finally, the simulation of each unit module and the whole loop system is carried out by using the analog integrated circuit design tools such as CADENCEN HSpice and SPECTRE, and the layout design of the whole loop system is completed. The simulation results show that the clock jitter is 2.27 psand the locking time is 3.3 渭 s when the clock generator outputs the 1.62GHz square wave signal at 25 鈩，
本文编号：2174381
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