双模单芯片UHF RFID读写器数字基带接收链路设计与实现

发布时间：2018-08-13 11:56

【摘要】：近年来,随着物联网产业的迅猛发展,射频识别技术(RFID)越来越受关注,并得到了广泛的应用和发展。在超高频频段,目前国际上主流的标准协议为ISO18000-6C,为适应RFID的发展和加快物联网的建设,我国也开始了协议的研究,并于2014年开始实施了UHF RFID国家标准GB/T29768-2013。因此,本项目意在研究一款既支持ISO 18000-6C国际标准协议,又支持国家标准GB/T29768-2013两种协议的UHF RFID读写器,既能满足国际市场的需求,又兼具本土产品的适用性,其具有很大的发展市场和意义。本文所做的便是该项目的一个子课题,双模单芯片UHF RFID读写器数字基带接收链路的设计与实现。首先,本文详细分析和对比ISO 18000-6C和GB/T29768-2013两种协议,包括发射链路、接收链路、通信指令以及防碰撞机制等,详细讨论接收链路。在此协议基础上,对整个数字基带进行系统分析,详细分析数字基带接收链路,并进行指标的设计以及整个数字基带接收链路的架构设计。接着,以模块化设计为主要方法,对数字基带接收链路和与接收链路相关的控制单元模块进行分析和设计,并进行verilog实现和功能仿真。数字基带接收链路模块包括码元同步模块、解码模块和CRC校验模块。读写器数字基带接收链路相关的控制单元模块包括协议控制信号处理单元、接口模块和接收FIFO单元。其中码元同步模块是整个数字基带接收链路的重点和难点,采用一种新颖的改进型的边沿过零检测型结构,在10 dB SNR的数字基带信号下能够正确同步和判决。该结构性能满足要求,具有面积资源消耗少、易实现、同步速度快等优点。最后,通过FPGA测试平台的搭建,采用Altera公司Stratix III系列的EP3SL150F1152C2与读写器射频模拟模块联合搭建成一套完整的读写器系统,来实际验证我们设计的数字基带接收链路,并将通过验证的数字基带接收链路在SMIC 0.13μm工艺上进行芯片实现。其中读写器数字基带接收链路版图大小为280228μm2,提取版图寄生参数后的仿真结果满足设计要求。
[Abstract]:In recent years, with the rapid development of the Internet of things industry, RFID technology (RFID) has attracted more and more attention, and has been widely used and developed. In UHF frequency band, ISO 18000-6C is the main international standard protocol at present. In order to adapt to the development of RFID and accelerate the construction of Internet of things, China has also begun to study the protocol, and has implemented the national standard of UHF RFID GB/ T29768-2013 in 2014. Therefore, the purpose of this project is to study a UHF RFID reader that supports both the ISO 18000-6C international standard agreement and the national standard GB/T29768-2013 protocol, which can meet the needs of the international market as well as the applicability of local products. It has great development market and significance. What this paper does is a sub-project of this project, the design and realization of digital baseband receiving link of dual-mode single-chip UHF RFID reader. Firstly, this paper analyzes and compares the ISO 18000-6C and GB/T29768-2013 protocols in detail, including transmitting link, receiving link, communication instruction and anti-collision mechanism, and discusses the receiving link in detail. On the basis of this protocol, the whole digital baseband is systematically analyzed, the digital baseband receiving link is analyzed in detail, the index is designed and the architecture of the whole digital baseband receiving link is designed. Then, the digital baseband receiving link and the control unit module related to the receiving link are analyzed and designed by modularization design, and the verilog implementation and function simulation are carried out. The digital baseband receiving link module includes symbol synchronization module, decoding module and CRC verification module. The control unit module of the reader digital baseband receiving link includes a protocol control signal processing unit, an interface module and a receiving FIFO unit. The symbol synchronization module is the focus and difficulty of the whole digital baseband receiving link. A novel improved edge zero-crossing detection structure is adopted, which can synchronize and judge correctly under the digital baseband signal of 10 dB SNR. The structure has the advantages of low area resource consumption, easy realization and high synchronization speed. Finally, through the construction of FPGA test platform and the combination of EP3SL150F1152C2 of Stratix III series of Altera company and RF analog module of reader, a complete reader system is built to verify the digital baseband receiving link that we designed. The verified digital baseband receiving link is implemented on SMIC 0.13 渭 m technology. The layout of the digital baseband receiving link of the reader is 280228 渭 m ~ 2. The simulation results after extracting the parasitic parameters of the layout meet the design requirements.
【学位授予单位】：湘潭大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TP391.44;TN402

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