基于门节点分级选择的CMOL电路单元快速容错映射
发布时间：2018-08-14 08:39
【摘要】：针对存在缺陷CMOL电路的单元容错映射问题,提出了一种分级选择电路门节点的容错映射方法.首先通过拓扑排序求出电路门的逻辑级;然后采用级间隔的方式进行选择,并对有缺陷连接的门节点进行惩罚,提高其被选择配置的概率.实验结果表明,与已有算法相比,该方法平均选择配置的门节点总数明显减少,在纳米二极管常开缺陷密度为40%、牺牲0.18%线长的情况下,CPU平均运行时间减少了30.68%.
[Abstract]:In order to solve the problem of cell fault-tolerant mapping in CMOL circuits with defects, a fault tolerant mapping method for hierarchical selection of gate nodes is proposed. First, the logic level of the circuit gate is obtained by topological sorting, and then the gate node with defective connection is punished by the method of stage interval to increase its probability of being selected and configured. The experimental results show that compared with the existing algorithms, the average number of gate nodes selected in this method is significantly reduced, and the average CPU running time is reduced by 30.68 when the defect density of the nanodiodes is 40 and 0.18% line length is sacrificed.
【作者单位】： 宁波大学信息科学与工程学院;
【基金】：国家自然科学基金(61571248,61501268) 浙江省自然科学基金(LQ15F040001) 宁波市自然科学基金(2015A610112)
【分类号】：TN40
，
本文编号：2182270
[Abstract]:In order to solve the problem of cell fault-tolerant mapping in CMOL circuits with defects, a fault tolerant mapping method for hierarchical selection of gate nodes is proposed. First, the logic level of the circuit gate is obtained by topological sorting, and then the gate node with defective connection is punished by the method of stage interval to increase its probability of being selected and configured. The experimental results show that compared with the existing algorithms, the average number of gate nodes selected in this method is significantly reduced, and the average CPU running time is reduced by 30.68 when the defect density of the nanodiodes is 40 and 0.18% line length is sacrificed.
【作者单位】： 宁波大学信息科学与工程学院;
【基金】：国家自然科学基金(61571248,61501268) 浙江省自然科学基金(LQ15F040001) 宁波市自然科学基金(2015A610112)
【分类号】：TN40
，
本文编号：2182270
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