一种快速关断沟槽型SOI LDMOS器件
发布时间：2018-08-18 16:11
【摘要】：围绕降低沟槽型SOI LDMOS功率器件的优值,提出了一种新型多栅沟槽SOI LDMOS器件(MG-TMOS)。与常规沟槽型SOI LDMOS(C-TMOS)器件相比,新型MG-TMOS器件在不牺牲击穿电压的同时,降低了器件开关切换时充放电的栅漏电荷和器件的比导通电阻。这是因为:1)新型MG-TMOS器件沟槽里的保护栅将器件的栅漏电容转换为器件的栅源电容和漏源电容,大幅度降低了器件的栅漏电荷;2)保护栅偏置电压的存在使得器件导通时会在沟槽底部形成一层低阻积累层,从而降低器件的导通电阻。仿真结果表明:该新型沟槽型SOI LDMOS器件的优值从常规器件的503.4mΩ·nC下降到406.6mΩ·nC,实现了器件的快速关断。
[Abstract]:A novel multi-gate grooved SOI LDMOS device (MG-TMOS) is proposed to reduce the superior value of grooved SOI LDMOS power device. Compared with conventional SOI LDMOS (C-TMOS devices, the novel MG-TMOS devices can reduce the gate leakage charge and discharge and the specific on-resistance of the devices without sacrificing the breakdown voltage. This is because the protection gate in the grooves of the new MG-TMOS device converts the device's gate leakage capacitance into the device's gate source capacitance and drain source capacitance. The gate leakage charge of the device is greatly reduced. The existence of the guard gate bias voltage causes the device to form a low resistance accumulation layer at the bottom of the groove when the device is on, thus reducing the on-resistance of the device. The simulation results show that the excellent value of the novel grooved SOI LDMOS device is reduced from 503.4 m 惟 NC to 406.6 m 惟 NC, and the fast turn-off of the device is realized.
【作者单位】： 西南交通大学信息科学与技术学院;
【基金】：国家自然科学基金资助项目(61404110)
【分类号】：TN386
本文编号：2189992
[Abstract]:A novel multi-gate grooved SOI LDMOS device (MG-TMOS) is proposed to reduce the superior value of grooved SOI LDMOS power device. Compared with conventional SOI LDMOS (C-TMOS devices, the novel MG-TMOS devices can reduce the gate leakage charge and discharge and the specific on-resistance of the devices without sacrificing the breakdown voltage. This is because the protection gate in the grooves of the new MG-TMOS device converts the device's gate leakage capacitance into the device's gate source capacitance and drain source capacitance. The gate leakage charge of the device is greatly reduced. The existence of the guard gate bias voltage causes the device to form a low resistance accumulation layer at the bottom of the groove when the device is on, thus reducing the on-resistance of the device. The simulation results show that the excellent value of the novel grooved SOI LDMOS device is reduced from 503.4 m 惟 NC to 406.6 m 惟 NC, and the fast turn-off of the device is realized.
【作者单位】： 西南交通大学信息科学与技术学院;
【基金】：国家自然科学基金资助项目(61404110)
【分类号】：TN386
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