10位Unary-R-2R型DAC性能研究与设计
发布时间：2018-08-22 07:13
【摘要】：数模转换器(DAC,Digital-to-Analog Converter)作为一种将数字信号转换为模拟信号的转换器,是信号处理系统中的关键模块之一。电流舵型DAC是主流的高速DAC结构,它常用于通信和多媒体领域。随着移动设备的快速发展,系统对芯片的低功耗性能要求越来越高。然而,电流舵型DAC中的单位电流源在极小的工作电流下匹配性会变差,导致电流舵型DAC性能的下降。Unary-R-2R型DAC通过电阻梯的分流特性产生低位电流,从而避免了DAC中的电流源工作电流过低,一定程度上保证了单位电流源的匹配程度。本文首先介绍了数模转换器的发展现状,简要比较了各式DAC的结构特点、工作原理及主要性能参数,介绍了Unary-R-2R型DAC的结构特点。根据Unary-R-2R型DAC的结构特点确定了DAC的分段方式,根据Unary-R-2R型DAC的工作原理建立了理想的行为级模型和相应的仿真平台。本文分析了电阻失配、电流源失配、有限输出阻抗和RC延迟效应这四个实际电路中存在的非理想因素,根据各个非理想因素的特性对理想的行为级模型做出修改。通过仿真平台,分别对四个非理想因素影响DAC性能的特点做出了研究。研究结果表明,电流源失配对DAC性能的影响最大,电阻失配仅影响静态性能,有限输出阻抗对动态性能的影响较大,RC延迟效应在寄生电容较大时对DAC动态性能影响明显。最后,利用MATLAB模型得到的结论基于TSMC 0.13μm 1P8M CMOS工艺设计了一个10位Unary-R-2R型数模转换器,并进行了相应的系统性能仿真。文中主要设计了基准源、单位电流源及R-2R电阻梯。其中,为了获得受温度影响小的基准电流,基准源采用带隙基准技术产生基准电压,通过压流转换形成基准电流;为了减小有限输出阻抗对电路性能的影响,在单位电流源中使用了共源共栅结构;在R-2R电阻梯部分通过使用多个多晶电阻构建电阻块,减小了各个电阻块之间的失配,降低了R-2R电阻梯的分流偏差对DAC静态性能的影响。系统仿真结果表明,本文设计的数模转换器最大DNL和INL小于0.5LSB。当输入信号频率为20MHz采样频率为300MHz时,DAC的信噪比为65.8d B,无杂散动态范围为62.36d B,有效位数为9.7533。
[Abstract]:As a kind of converter to convert digital signal to analog signal, DACY Digital-to-Analog Converter is one of the key modules in signal processing system. Current-rudder DAC is a mainstream high-speed DAC architecture, which is often used in the field of communication and multimedia. With the rapid development of mobile devices, the low power performance of the system is becoming more and more important. However, the matching of unit current sources in the current-rudder type DAC will become worse under the minimal operating current, which leads to the decline of the performance of the current-rudder type DAC. Unary-R-2R type DAC generates low current through the shunt characteristics of the resistor ladder. Thus the current source working current in DAC is not too low and the matching degree of unit current source is ensured to some extent. This paper first introduces the development of digital-to-analog converters, briefly compares the structural characteristics, working principles and main performance parameters of various DAC, and introduces the structural characteristics of Unary-R-2R type DAC. According to the structural characteristics of Unary-R-2R type DAC, the segmented mode of DAC is determined, and the ideal behavior level model and corresponding simulation platform are established according to the working principle of Unary-R-2R type DAC. In this paper, the nonideal factors in four practical circuits, resistance mismatch, current source mismatch, finite output impedance and RC delay effect, are analyzed, and the ideal behavior level model is modified according to the characteristics of each non-ideal factor. Based on the simulation platform, the characteristics of four non-ideal factors affecting DAC performance are studied. The results show that the current source mismatch has the greatest influence on the DAC performance, the resistance mismatch only affects the static performance, and the limited output impedance has a greater effect on the dynamic performance of DAC. The RC delay effect has a significant effect on the dynamic performance of DAC when the parasitic capacitance is large. Finally, a 10-bit Unary-R-2R digital-to-analog converter is designed based on the TSMC 0.13 渭 m 1P8M CMOS process based on the conclusion of the MATLAB model, and the corresponding system performance simulation is carried out. In this paper, reference source, unit current source and R-2R resistance ladder are designed. In order to obtain the reference current which is less affected by temperature, the reference voltage is generated by bandgap reference technique, and the reference current is formed by voltage-current conversion, and in order to reduce the effect of limited output impedance on circuit performance, The common gate structure is used in the unit current source, and the resistance block is constructed by using multiple polycrystalline resistors in the R-2R resistor ladder, which reduces the mismatch between the resistor blocks and the influence of the shunt deviation of the R-2R resistor ladder on the static performance of DAC. The simulation results show that the maximum DNL and INL of the digital-to-analog converter designed in this paper are less than 0.5 LSB. When the input signal frequency is 20MHz sampling frequency, the signal-to-noise ratio is 65.8 dB, the non-spurious dynamic range is 62.36 dB, and the effective bit number is 9.7533.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
本文编号：2196353
[Abstract]:As a kind of converter to convert digital signal to analog signal, DACY Digital-to-Analog Converter is one of the key modules in signal processing system. Current-rudder DAC is a mainstream high-speed DAC architecture, which is often used in the field of communication and multimedia. With the rapid development of mobile devices, the low power performance of the system is becoming more and more important. However, the matching of unit current sources in the current-rudder type DAC will become worse under the minimal operating current, which leads to the decline of the performance of the current-rudder type DAC. Unary-R-2R type DAC generates low current through the shunt characteristics of the resistor ladder. Thus the current source working current in DAC is not too low and the matching degree of unit current source is ensured to some extent. This paper first introduces the development of digital-to-analog converters, briefly compares the structural characteristics, working principles and main performance parameters of various DAC, and introduces the structural characteristics of Unary-R-2R type DAC. According to the structural characteristics of Unary-R-2R type DAC, the segmented mode of DAC is determined, and the ideal behavior level model and corresponding simulation platform are established according to the working principle of Unary-R-2R type DAC. In this paper, the nonideal factors in four practical circuits, resistance mismatch, current source mismatch, finite output impedance and RC delay effect, are analyzed, and the ideal behavior level model is modified according to the characteristics of each non-ideal factor. Based on the simulation platform, the characteristics of four non-ideal factors affecting DAC performance are studied. The results show that the current source mismatch has the greatest influence on the DAC performance, the resistance mismatch only affects the static performance, and the limited output impedance has a greater effect on the dynamic performance of DAC. The RC delay effect has a significant effect on the dynamic performance of DAC when the parasitic capacitance is large. Finally, a 10-bit Unary-R-2R digital-to-analog converter is designed based on the TSMC 0.13 渭 m 1P8M CMOS process based on the conclusion of the MATLAB model, and the corresponding system performance simulation is carried out. In this paper, reference source, unit current source and R-2R resistance ladder are designed. In order to obtain the reference current which is less affected by temperature, the reference voltage is generated by bandgap reference technique, and the reference current is formed by voltage-current conversion, and in order to reduce the effect of limited output impedance on circuit performance, The common gate structure is used in the unit current source, and the resistance block is constructed by using multiple polycrystalline resistors in the R-2R resistor ladder, which reduces the mismatch between the resistor blocks and the influence of the shunt deviation of the R-2R resistor ladder on the static performance of DAC. The simulation results show that the maximum DNL and INL of the digital-to-analog converter designed in this paper are less than 0.5 LSB. When the input signal frequency is 20MHz sampling frequency, the signal-to-noise ratio is 65.8 dB, the non-spurious dynamic range is 62.36 dB, and the effective bit number is 9.7533.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
【参考文献】
相关硕士学位论文 前1条
1 吴苗松;14bit、30Msps自校准分段式电流舵DAC的设计[D];电子科技大学;2005年
，本文编号：2196353
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