低功耗逐次逼近型CMOS模数转换器的研究

发布时间：2018-08-22 07:53

【摘要】：模数转换器(ADC:Analog-to-Digital Converter)作为信号链路中必不可少的一个模块单元,被广泛应用在各种片上系统中。此外,在无线传感网络、生命监测和便携式娱乐等低功耗应用场合中,电池的寿命及单次供电持续时间也成为一个亟待解决的问题。随着工艺特征尺寸的不断减小,模拟电路的设计变得越来越困难。和过采样(Delta-Sigma)ADC、流水线型模数转换器(pipeline ADC)相比,逐次逼近型模数转换器(SAR ADC)由于结构简单、功耗低、易于集成等优点成为了研究的热点。本文在理论创新方面主要的工作有:(1)提出了能够显著优化低功耗逐次逼近型模数转换器整体功耗的非对称电荷补偿型开关时序,并对该时序的开关功耗、复位功耗和线性度进行了分析。和单调型开关时序相比,该开关时序能够降低93.8%的开关功耗。如果将复位功耗考虑在内,采用该开关时序的电容型DAC的总功耗(开关功耗与复位功耗之和)将优化到18.4%。在电容具有相同匹配精度的前提下,本文提出的非对称电荷补偿型开关时序的最大微分非线性误差满足的高斯分布的方差仅仅是单调型开关时序对应的最大微分非线性误差满足的高斯分布的1/2。通过采用节能型电荷补偿型开关时序,基于SMIC0.18-μm CMOS工艺,本文设计实现了一款0.6-V、10位、20kS/s的超低功耗逐次逼近型模数转换器。测试结果显示,在奈奎斯特输入条件下,该ADC达到9.4位的有效位数,功耗仅为38nW。(2)对工作在弱反型区的动态锁存比较器的输入失调电压随比较器共模输入电平的变化关系进行了理论推导和仿真验证。根据理论分析得到的结果,在0.6-V的电源电压下,通过对比较器中晶体管尺寸进行优化,当比较器输入共模电平从300mV变化到450mV时,输入失调电压的3×σ变化幅度为0.15mV,仅为1/8LSB。(3)对限制逐次逼近型模数转换器采样速度的因素进行了分析,通过对逐次逼近型模数转换器中电容型DAC的结构进行改进,提出了一种能够有效改善逐次逼近型模数转换器采样速度的新型DAC结构。基于SMIC 65-nm CMOS工艺,本文设计了一款1.2-V、10位、300MS/s的低功耗SAR ADC。介于功耗、芯片面积和采样速度等方面的折衷考虑,该逐次逼近型模数转换器采用了两级子DAC,其中第一级子DAC精度为5位,第二级子DAC精度为10位。和传统逐次逼近型模数转换器的结构相比,电路规模仅增加了32个单位电容和74个门电路的小规模数字逻辑。后仿真结果显示,在奈奎斯特输入条件下,该模数转换器的有效位数可达到9.67位,功耗仅为1.27mW。
[Abstract]:Analog-to-digital converter (ADC:Analog-to-Digital Converter), as a necessary module unit in signal link, is widely used in various on-chip systems. In addition, in wireless sensor networks, life monitoring, portable entertainment and other low-power applications, battery life and single power supply duration has become a problem to be solved. The design of analog circuit becomes more and more difficult with the decreasing of process characteristic size. Compared with over-sampling (Delta-Sigma) ADC and pipelined ADC (pipeline ADC), successive approximation analog-to-digital converter (SAR ADC) has become a hot research area because of its simple structure, low power consumption and easy integration. The main work of this paper is as follows: (1) A series of asymmetric charge compensated switches, which can significantly optimize the overall power consumption of a low power successive approximation type A / D converter, are proposed, and the switching power consumption of the sequence is also discussed. Reset power consumption and linearity are analyzed. Compared with the monotonic switch sequence, the switching sequence can reduce the switching power by 93.8%. If the reset power is taken into account, the total power consumption (the sum of switching power and reset power) of the capacitive DAC using the switch timing will be optimized to 18.4. If the capacitance has the same matching precision, In this paper, the variance of the Gao Si distribution satisfied by the maximum differential nonlinear error of the asymmetric charge compensated switching sequence is only 1 / 2 of the Gao Si distribution satisfied by the maximal differential nonlinear error corresponding to the monotonic switch sequence. Based on the SMIC 0.18- 渭 m CMOS process, an ultra-low power successive approximation analog-to-digital converter is designed and implemented in this paper. The test results show that the ADC reaches a significant number of 9. 4 bits under Nyquist input conditions. (2) the relationship between input offset voltage and common-mode input level of dynamic latch comparator operating in weak inversion region is deduced theoretically and verified by simulation. According to the results of theoretical analysis, by optimizing the size of transistors in comparator at 0.6-V power supply voltage, when the input common-mode level of comparator changes from 300mV to 450mV, The amplitude of 3 脳蟽 input offset voltage is 0.15 MV, which is only 1 / 8 LSB. (3) the factors that limit the sampling speed of successive approximation analog-to-digital converters are analyzed, and the structure of capacitive DAC in successive approximation analog-to-digital converters is improved. This paper presents a novel DAC structure which can effectively improve the sampling speed of successive approximation A / D converters. Based on SMIC 65-nm CMOS process, this paper designs a low power SAR ADCs with 1. 2-V 10 bits and 300 MS / s. Considering the tradeoff among power consumption, chip area and sampling speed, the successive approximation analog-to-digital converter uses a two-stage sub-DAC, in which the first sub-DAC accuracy is 5 bits and the second stage sub-DAC accuracy is 10 bits. Compared with the structure of the traditional successive approximation analog-to-digital converter, the size of the circuit increases only 32 unit capacitors and 74 gates of the small-scale digital logic. The post-simulation results show that the effective bit number of the ADC can reach 9.67 bits under Nyquist input condition, and the power consumption is only 1.27 MW.
【学位授予单位】：西安电子科技大学
【学位级别】：博士
【学位授予年份】：2015
【分类号】：TN792

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