YHFT-XX芯片低功耗可测性设计及优化
发布时间：2018-08-22 14:26
【摘要】：随着集成电路设计规模增大、复杂度提高、设计周期缩短,芯片测试面临诸多问题需要解决,已成为集成电路发展的瓶颈,因此可测性设计(Design For testability,DFT)在芯片设计中的作用越来越重要。要实现完善的测试,需要考虑多方面测试要求,如面积开销、测试功耗、额外引脚需求等,而选择适用的测试策略就更为重要,合理应用DFT设计中的各种策略,从测试角度而言,可提高芯片的可测性、提高故障覆盖率、降低硬件开销及测试功耗等;从功能设计角度而言,合适的测试策略可使测试对功能的影响降到最低。本文针对YHFT-XX芯片可测试设计的需求,在降低测试功耗同时对可测性设计方法进行分析和结构优化,基于低功耗分块测试技术,在芯片顶层设计调度控制器管理测试时钟及MBIST测试启动信号,进一步降低测试功耗,在满足测试质量要求以及降低测试成本的同时保证芯片质量和上市时间。本文主要工作如下:一、分析YHFT-XX芯片在可测性方面面临的问题,基于低功耗分块测试提出解决方案。为了降低扫描测试中组合逻辑功耗,对部分扫描逻辑插入增强型阻隔门。针对芯片低功耗分块测试时,内部模块原始端口不可直接访问问题,提出旁路结构和Wrapper测试环共享两种方案,实现对被测模块端口的测试访问,且在YHFT-XX芯片中获得良好效果,与传统Wrapper结构相比,Wrapper共享结构面积可减少61.79%,旁路结构可减少87.60%。二、优化存储体内建自测试(Memory Build-In Self Test,MBIST)设计中的存储体旁路结构节省面积开销,减少时序单元逻辑数量,扫描测试功耗也略有降低,尤其设计中包含大量存储体时,可以有效降低硬件开销,本文中的方法可根据具体电路结构和测试覆盖率要求执行优化方案,本文实验中FFT_Ram_inst存储体,在三级异或时面积节省50.68%,在FFT_top模块中扫描测试功耗降低约1.53%。三、在芯片顶层采用测试调度控制器,实现低功耗测试,并对可测性技术中的扫描测试和MBIST进行统一测试管理,该控制器能够灵活控制测试启动和测试结果反馈,在测试结果反馈处,设计了MBIST控制器输出观测链,在机台测试时可实现对故障存储体定位。通过测试策略对控制器的模式链配置,不仅可以减少测试引脚,而且达到降低测试功耗目的。论文中提出的优化方案和低功耗测试控制已经应用到YHFT-XX芯片可测性设计中,且表现出良好的效果。论文中的研究成果对电子设计自动化工具的开发也具有一定的参考价值。
[Abstract]:With the enlargement of IC design scale, the increase of complexity, the shortening of design cycle, the chip testing faces many problems to be solved, which has become the bottleneck of IC development. Therefore, testability design (Design For) plays an increasingly important role in chip design. In order to realize perfect test, we need to consider many kinds of test requirements, such as area overhead, test power consumption, extra pin requirement and so on. It is more important to choose suitable test strategy. From the point of view of testing, it can improve the testability of the chip, improve the fault coverage, reduce the hardware overhead and test power consumption, etc. From the point of view of function design, the appropriate test strategy can minimize the impact of testing on the function. According to the requirement of YHFT-XX chip testability design, this paper analyzes and optimizes the testability design method while reducing the test power consumption. A scheduling controller is designed at the top of the chip to manage the test clock and the MBIST test start signal to further reduce the test power consumption and ensure the chip quality and the time to market while satisfying the test quality requirements and reducing the test cost. The main work of this paper is as follows: firstly, the problems in testability of YHFT-XX chip are analyzed, and a solution based on low power block testing is proposed. In order to reduce the power consumption of combinational logic in scanning test, an enhanced barrier gate is inserted into partial scan logic. In order to solve the problem that the original port of the internal module can not be accessed directly when the chip is divided into blocks with low power consumption, a bypass structure and a Wrapper test ring sharing scheme are proposed to realize the test access to the port of the module under test, and good results are obtained in the YHFT-XX chip. Compared with the traditional Wrapper structure, the area of the shared structure can be reduced by 61.79 and the bypass structure by 87.60. Secondly, the memory bypass structure in the design of Memory Build-In Self Test self-test (MBIST) is optimized to save area overhead, reduce the number of sequential unit logic, and reduce the power consumption of scanning test slightly, especially when a large number of storage bodies are included in the design. The method in this paper can carry out the optimization scheme according to the specific circuit structure and test coverage requirements. In the experiment, the FFT_Ram_inst storage can save 50.68 points in the three-level XOR time area, and the power consumption of scanning test in the FFT_top module can be reduced by 1.53. Thirdly, a test scheduling controller is adopted at the top of the chip to realize low power test, and the scanning test and MBIST in testability technology are managed uniformly. The controller can control test startup and feedback test results flexibly. At the feedback point of test results, the output observation chain of MBIST controller is designed, and the fault storage can be located when the machine is tested. The mode chain configuration of the controller by test strategy can not only reduce the test pin, but also reduce the test power consumption. The proposed optimization scheme and low power test control have been applied to the testability design of YHFT-XX chip and show good results. The research results in this paper also have some reference value for the development of electronic design automation tools.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402
本文编号：2197369
[Abstract]:With the enlargement of IC design scale, the increase of complexity, the shortening of design cycle, the chip testing faces many problems to be solved, which has become the bottleneck of IC development. Therefore, testability design (Design For) plays an increasingly important role in chip design. In order to realize perfect test, we need to consider many kinds of test requirements, such as area overhead, test power consumption, extra pin requirement and so on. It is more important to choose suitable test strategy. From the point of view of testing, it can improve the testability of the chip, improve the fault coverage, reduce the hardware overhead and test power consumption, etc. From the point of view of function design, the appropriate test strategy can minimize the impact of testing on the function. According to the requirement of YHFT-XX chip testability design, this paper analyzes and optimizes the testability design method while reducing the test power consumption. A scheduling controller is designed at the top of the chip to manage the test clock and the MBIST test start signal to further reduce the test power consumption and ensure the chip quality and the time to market while satisfying the test quality requirements and reducing the test cost. The main work of this paper is as follows: firstly, the problems in testability of YHFT-XX chip are analyzed, and a solution based on low power block testing is proposed. In order to reduce the power consumption of combinational logic in scanning test, an enhanced barrier gate is inserted into partial scan logic. In order to solve the problem that the original port of the internal module can not be accessed directly when the chip is divided into blocks with low power consumption, a bypass structure and a Wrapper test ring sharing scheme are proposed to realize the test access to the port of the module under test, and good results are obtained in the YHFT-XX chip. Compared with the traditional Wrapper structure, the area of the shared structure can be reduced by 61.79 and the bypass structure by 87.60. Secondly, the memory bypass structure in the design of Memory Build-In Self Test self-test (MBIST) is optimized to save area overhead, reduce the number of sequential unit logic, and reduce the power consumption of scanning test slightly, especially when a large number of storage bodies are included in the design. The method in this paper can carry out the optimization scheme according to the specific circuit structure and test coverage requirements. In the experiment, the FFT_Ram_inst storage can save 50.68 points in the three-level XOR time area, and the power consumption of scanning test in the FFT_top module can be reduced by 1.53. Thirdly, a test scheduling controller is adopted at the top of the chip to realize low power test, and the scanning test and MBIST in testability technology are managed uniformly. The controller can control test startup and feedback test results flexibly. At the feedback point of test results, the output observation chain of MBIST controller is designed, and the fault storage can be located when the machine is tested. The mode chain configuration of the controller by test strategy can not only reduce the test pin, but also reduce the test power consumption. The proposed optimization scheme and low power test control have been applied to the testability design of YHFT-XX chip and show good results. The research results in this paper also have some reference value for the development of electronic design automation tools.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402
【参考文献】
相关期刊论文 前4条
1 王伟;韩银和;胡瑜;李晓维;张佑生;;一种有效的低功耗扫描测试结构——PowerCut[J];计算机研究与发展;2007年03期
2 成立,王振宇,高平,祝俊;VLSI电路可测性设计技术及其应用综述[J];半导体技术;2004年05期
3 陆重阳,卢东华,文爱军;IP技术在SOC中的地位及应用[J];微电子技术;2002年04期
4 李兆麟,叶以正;全扫描设计中多扫描链的构造[J];电子学报;2000年02期
，本文编号：2197369
本文链接：https://www.wllwen.com/kejilunwen/dianzigongchenglunwen/2197369.html
