一种低功耗低成本测试图形的生成方法

发布时间：2018-08-24 12:51

【摘要】：针对半导体器件特征尺寸小、集成电路集成度和复杂度高导致的芯片测试功耗高、面积开销和测试数据量大等问题,提出了一种带广播结构的低功耗低成本内建自测试的测试图形生成方法,给出了硬件实现方式和测试方案。首先,该方法通过一个异或网络将线性反馈移位寄存器(LFSR)结构和Johnson计数器相结合,产生具有多维单输入跳变(MSIC)特性的测试向量;然后,通过复用测试生成结构,广播电路将测试向量扩展为能够填充更多扫描链的基于广播的多维单输入跳变(BMSIC)测试图形,从而减小了测试图形生成电路的面积开销;最后,以ISCAS’89系列中较大的5款电路为对象实验,结果表明,与MSIC测试生成电路相比,BMSIC测试图形生成方法可在确保低功耗高故障覆盖率基础上,减小50%左右的电路面积开销。
[Abstract]:In order to solve the problems such as low characteristic size of semiconductor devices, high integration and complexity of integrated circuits, high chip test power consumption, large area overhead and large amount of test data, etc. A low power and low cost test graph generation method with broadcast architecture is proposed. The hardware implementation and test scheme are given. Firstly, the method combines the linear feedback shift register (LFSR) structure with the Johnson counter through an XOR network to generate the test vector with multi-dimensional single-input jump (MSIC), and then the structure is generated by multiplexing test. The broadcast circuit extends the test vector to a broadcast-based multi-dimensional single-input jump (BMSIC) test graph that can fill in more scan chains, thus reducing the area overhead of the test graph generation circuit. The experimental results of five larger circuits in ISCAS'89 series show that compared with the MSIC test generation circuit, the method can reduce the area overhead by about 50% on the basis of ensuring low power consumption and high fault coverage.
【作者单位】：西安交通大学微电子学院;
【基金】：国家自然科学基金资助项目(61474093)
【分类号】：TN407

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