集成电路静电保护网络及器件特性研究和设计优化
发布时间：2018-08-24 19:55
【摘要】：随着微电子技术的不断发展,特征尺寸的降低和新工艺技术的引入,集成电路和系统对ESD应力越来越敏感。本文在0.35um的工艺下,分析了常见的ESD保护器件的工作特性及仿真结果,设计出基本箝位电路网络。以中芯国际生产的芯片JSR26C32以及TI公司的CD54HC123F3A测试结果,分析失效原因并且提出改进措施。主要的研究内容如下:论文针对ESD的基本概念进行了分析。对四种的ESD保护器件的工作原理进行了研究与仿真。重点对ggNMOS在ESD脉冲下的电流分布及热分布进行仿真。对比了SCR和LVTSCR结构的触发电压以及保持电压。分析了依靠RC和有源器件开启的箝位网络。利用HSPICE仿真分析了不同大小的栅漏耦合电容对HBM和MM应力下箝位电压的影响,对实际的防护电路设计参数的选取提供了理论支持。针对多电源领域的应用,改进了一款箝位电路。该电路具有两倍箝位电压、堆叠MOS构成的高电压容限的箝位电路,并且仿真分析得到的箝位电压为10V验证了理论;最后分析了两级ESD保护电路在基于ESD轨和局部箝位两种防护策略的应用,仿真验证了一款三端二极管结构构成的两级保护电路的实际防护效果。设计了针对上海航天技术研究院提供的JSR26C32以及TI公司的CD54HC123F3A的实验方法。研究了两种芯片针对不同的管脚的ESD保护电路原理、尺寸及布局设计。设计了针对三种测试模型的测试方案,起始电压及步长的选择,并且确定了该芯片的失效阈值ESDV。提出了三种判断芯片失效的标准。通过光学显微镜及其他设备的帮助,在加电状态下找出失效点。继续剖片找出失效位置,结合电路逻辑图与版图布局给出失效的分析结果。参考国内外的文献提出器件及布局的改进措施。综上所述,本文以常见的ESD保护器件和箝位网络的设计方法,在亚微米尺度分析ESD防护器件ggNMOS和SCR的性能。分析仿真了箝位网络及针对高电压容限的电路设计。结合实际芯片的电路原理和布局,分析了两种芯片的失效原因,为后续的ESD改进设计提供了指导。
[Abstract]:With the development of microelectronics, the reduction of feature size and the introduction of new technology, integrated circuits and systems are more and more sensitive to ESD stress. In this paper, the operating characteristics and simulation results of common ESD protection devices are analyzed under the technology of 0.35um, and the basic clamping circuit network is designed. Based on the JSR26C32 chip produced by SMIC and the CD54HC123F3A test results of TI Company, the causes of failure are analyzed and the improvement measures are put forward. The main research contents are as follows: the basic concept of ESD is analyzed in this paper. The working principle of four kinds of ESD protection devices is studied and simulated. The current distribution and heat distribution of ggNMOS under ESD pulse are simulated. The trigger voltage and hold voltage of SCR and LVTSCR are compared. The clamping network which is opened by RC and active device is analyzed. The effects of different sizes of gate leakage coupling capacitors on clamping voltage under HBM and MM stress are analyzed by HSPICE simulation, which provides theoretical support for the selection of design parameters of practical protection circuits. A clamping circuit is improved for the application of multi-power supply field. The circuit has double clamping voltage and high voltage tolerance clamping circuit composed of stacked MOS. The simulation results show that the clamping voltage is 10V. Finally, the application of two-stage ESD protection circuit based on ESD rail and local clamping is analyzed, and the actual protection effect of a three-terminal diode structure is verified by simulation. The experimental methods for JSR26C32 provided by Shanghai Aerospace Technology Research Institute and CD54HC123F3A of TI Company are designed. The principle, size and layout of ESD protection circuit for different pins are studied. The test scheme for three test models, the choice of starting voltage and step size are designed, and the failure threshold ESDV. of the chip is determined. Three criteria for judging chip failure are proposed. Through the help of optical microscope and other equipment to find out the failure point in the power-on state. Continue to slice to find out the failure location, combined with the circuit logic diagram and layout to give the failure analysis results. The improvement measures of device and layout are put forward with reference to the literature at home and abroad. To sum up, the performance of ESD protection devices ggNMOS and SCR is analyzed at submicron scale by the common design methods of ESD protection devices and clamping networks. The clamp network and the circuit design for high voltage tolerance are analyzed and simulated. Combined with the circuit principle and layout of the actual chip, the failure reasons of the two kinds of chips are analyzed, which provides guidance for improving the design of ESD in the future.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402
本文编号：2201862
[Abstract]:With the development of microelectronics, the reduction of feature size and the introduction of new technology, integrated circuits and systems are more and more sensitive to ESD stress. In this paper, the operating characteristics and simulation results of common ESD protection devices are analyzed under the technology of 0.35um, and the basic clamping circuit network is designed. Based on the JSR26C32 chip produced by SMIC and the CD54HC123F3A test results of TI Company, the causes of failure are analyzed and the improvement measures are put forward. The main research contents are as follows: the basic concept of ESD is analyzed in this paper. The working principle of four kinds of ESD protection devices is studied and simulated. The current distribution and heat distribution of ggNMOS under ESD pulse are simulated. The trigger voltage and hold voltage of SCR and LVTSCR are compared. The clamping network which is opened by RC and active device is analyzed. The effects of different sizes of gate leakage coupling capacitors on clamping voltage under HBM and MM stress are analyzed by HSPICE simulation, which provides theoretical support for the selection of design parameters of practical protection circuits. A clamping circuit is improved for the application of multi-power supply field. The circuit has double clamping voltage and high voltage tolerance clamping circuit composed of stacked MOS. The simulation results show that the clamping voltage is 10V. Finally, the application of two-stage ESD protection circuit based on ESD rail and local clamping is analyzed, and the actual protection effect of a three-terminal diode structure is verified by simulation. The experimental methods for JSR26C32 provided by Shanghai Aerospace Technology Research Institute and CD54HC123F3A of TI Company are designed. The principle, size and layout of ESD protection circuit for different pins are studied. The test scheme for three test models, the choice of starting voltage and step size are designed, and the failure threshold ESDV. of the chip is determined. Three criteria for judging chip failure are proposed. Through the help of optical microscope and other equipment to find out the failure point in the power-on state. Continue to slice to find out the failure location, combined with the circuit logic diagram and layout to give the failure analysis results. The improvement measures of device and layout are put forward with reference to the literature at home and abroad. To sum up, the performance of ESD protection devices ggNMOS and SCR is analyzed at submicron scale by the common design methods of ESD protection devices and clamping networks. The clamp network and the circuit design for high voltage tolerance are analyzed and simulated. Combined with the circuit principle and layout of the actual chip, the failure reasons of the two kinds of chips are analyzed, which provides guidance for improving the design of ESD in the future.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402
【参考文献】
相关期刊论文 前1条
1 朱科翰;于宗光;董树荣;韩雁;;0.18μm混合信号RFCMOS工艺中新型低触发电压双向SCR静电防护器件的设计(英文)[J];半导体学报;2008年11期
，本文编号：2201862
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