针对片上网络的低功耗互连设计

发布时间：2018-08-26 18:08

【摘要】：片上网络(NoC)是一种用于多处理器片上系统(MPSoC)的新型通信方法。该技术采用基于网络通讯的系统架构,不仅提高了通信效率,而且改善了可扩展性。同时,片上网络的引入有效地解决了传统的总线式SoC中出现的全局同步、带宽受限和功耗等问题。然而,随着集成电路工艺地逐步发展,特别是进入深亚微米工艺以后,NoC中互连结构引起的串扰等非理想效应带来了功耗、延时和可靠性等一系列问题。因此如何设计高速低功耗的NoC互连结构成为片上网络设计研究的热点之一。针对NoC中互连的功耗问题,提出了一种新型具有抑制串扰能力的低功耗编码——AGM。该编码的低功耗部分采用在低功耗自校准编码(SCG)的基础上改进得到的GM编码。同时,为了提高编码抑制串扰的能力引入时间编码技术。该编码的编解码器结构中还加入了并串/串并转换电路,通过减少互连线数量的方式降低互连功耗和节约布线资源。仿真结果表明,对于32bit随机数据源,AGM编码将互连线功耗降低了37.51%。为了进一步降低NoC的互连功耗,采用低功耗编码与低摆幅技术结合的设计方案。在发送电路中,先进行AGM低功耗编码,再采用一种基于电荷分享的电容型低摆幅发送电路(CCS)将数据发送出去。AGM编码有效地降低数据的翻转率,CCS电路将电容预加重型技术和电荷分享型技术相结合,不但降低了数据翻转的摆幅,而且使得信号在“0→1”跳变时无需从VDD获取能量,从而使互连线动态功耗直接减半,同时该电路还继承了电容预加重型电路的高带宽优点。在接收电路中,利用AC耦合电阻反馈反相器(CRFI)将信号偏置在VDD/2附近,同时转换为RZ脉冲信号。最后通过迟滞比较器将信号还原为全摆幅信号,并通过AGM解码器还原数据信息。基于SMIC 65nm工艺,采用Cadence IC610软件对其进行仿真,结果表明,CCS电路和AGM编码结合的方式能够有效的降低互连线上的功耗,同时提高了其抑制串扰的能力。相比于不使用AGM编码的全摆幅电路,单独使用AGM编码和CCS低摆幅电路在降低功耗方面分别为40%和72%左右,而采用AGM编码和CCS低摆幅电路结合的方式,其功耗下降了82%左右。同时由于数据抑制串扰能力的提高,数据最大传输速率进一步提高。
[Abstract]:NoC (NoC) is a new communication method for multiprocessor on-chip systems (MPSoC). This technology uses a network-based communication architecture, which not only improves communication efficiency, but also improves scalability. At the same time, the introduction of NoC effectively solves the global synchronization, bandwidth constraints and bandwidth limitations in the traditional bus-based SoC. However, with the development of IC technology, especially deep submicron technology, the crosstalk caused by interconnection structure in NoC brings a series of problems, such as power consumption, delay and reliability. Therefore, how to design high-speed and low-power interconnection structure of NoC has become a hot topic in NoC design and research. One. Aiming at the problem of interconnection power consumption in NoC, a novel low-power coding with crosstalk suppression capability, AGM, is proposed. The low-power part of the coding adopts GM coding improved on the basis of low-power self-calibration coding (SCG). At the same time, time coding technology is introduced to improve the ability of coding to suppress crosstalk. In order to reduce the interconnection power consumption and save wiring resources, parallel-series/series-parallel converter circuit is added to the codec structure. Simulation results show that AGM coding reduces the interconnection power consumption by 37.51% for 32 bit random data sources. In order to further reduce the interconnection power consumption of NoC, low power coding and low swing are adopted. In the transmitting circuit, AGM low-power coding is used first, and then a capacitive low-swing transmitting circuit based on charge-sharing (CCS) is used to transmit the data. AGM coding can effectively reduce the data turnover rate. CCS circuit combines capacitive pre-weighting technology with charge-sharing technology, which not only reduces the number of data The swing amplitude is reversed so that the signal does not need to get energy from the VDD during the "0_1" jump, thus reducing the interconnect dynamic power consumption by half directly. The circuit also inherits the high bandwidth advantage of the capacitor pre-weighting circuit. In the receiving circuit, the AC coupled resistance feedback inverter (CRFI) is used to bias the signal near the VDD/2 while reversing. Finally, the signal is reduced to full swing signal by hysteresis comparator, and the data information is restored by AGM decoder. Based on SMIC 65nm process, the simulation is carried out by Cadence IC610 software. The results show that the combination of CCS circuit and AGM coding can effectively reduce the power consumption of interconnects, and improve its performance. Compared with the full swing circuit without AGM coding, the power consumption of AGM coding and CCS low swing circuit is reduced by 40% and 72% respectively, while the power consumption of AGM coding and CCS low swing circuit is reduced by 82%. The transmission rate is further improved.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

【相似文献】