2-2MASH结构Sigma-Delta调制器设计
发布时间：2018-08-28 06:31
【摘要】：由于SOC芯片方向最近几年的快速发展,高精度、低功耗的模数转换器芯片越来越受到重视。在此背景下,本论文是为了实现高精度、低功耗、宽输入摆幅的模数转换器。在当前大规模集成电路工艺条件下,Sigma-Delta调制器是一种可以实现高分辨率模数转换器的有效方式,由于结合过采样、噪声整形技术,使用Sigma-Delta调制器的模数转换器能够实现16位以上的分辨率。这种结构不容易受到模拟电路非理想因素的影响,在当前工艺条件下,可以相对容易实现低成本、高性能的模数转换器。但Sigma-Delta ADC难以转换高速信号,而且模拟电路难度的降低增加了抽取滤波器的设计难度。本论文Sigma-Delta调制器主要从高精度、低功耗以及宽输入摆幅这几个方向深入研究。高阶Sigma-Delta调制器需要考虑稳定性问题,为了保证系统的稳定性,本论文Sigma-Delta调制器采用2-2MASH结构。为了减小1/f噪声和失调噪声,调制器第一级的积分器采用了斩波稳定技术,通过MATLAB软件建模和系统仿真,得到了调制器所需的前馈因子、反馈因子和积分器增益因子,采用一组全新设计的系数,使得调制器的过载输入电平几乎达到了满摆幅。为了符合应用的易携带型,调制器芯片采用低功耗的设计思路,从而使整个系统有最低功耗。通过本次设计,形成了从系统建模、电路设计、版图设计到流片的电路设计流程。本论文调制器采用全差分开关电容结构,采用了MXIC的0.5μm L50w CMOS工艺实现Sigma-Delta调制器,电源电压为5V,仿真得到在信号带宽为7.8KHz,采样频率为1MHz条件下,调制器的输入摆幅为±4V,最高信噪比为111.3d B,有效位数约为18位,功耗约为6.6m W,该Sigma-Delta调制器适合对精度、功耗、输入摆幅要求较高的模数转换器。
[Abstract]:Due to the rapid development of SOC chips in recent years, high precision and low power ADC chips have attracted more and more attention. In this context, the purpose of this paper is to achieve high precision, low power consumption, wide input swing A / D converter. Sigma-Delta modulator is an effective way to realize high resolution A / D converter under the current LSI technology. The A / D converter using Sigma-Delta modulator can achieve 16 bits or more resolution. This structure is not easily affected by the non-ideal factors of analog circuits. Under the current technological conditions, it is relatively easy to achieve low-cost, high-performance analog-to-digital converters. However, it is difficult for Sigma-Delta ADC to convert high speed signal, and the difficulty of analog circuit increases the design difficulty of decimation filter. In this paper, the Sigma-Delta modulator is mainly studied in the aspects of high precision, low power consumption and wide input swing. The high order Sigma-Delta modulator needs to consider the stability problem. In order to ensure the stability of the system, the 2-2MASH structure is adopted in the Sigma-Delta modulator. In order to reduce 1 / f noise and offset noise, chopper stabilization technique is used in the integrator of the first stage of the modulator. The feedforward factor, feedback factor and integrator gain factor are obtained by MATLAB software modeling and system simulation. By using a new set of design coefficients, the overload input level of the modulator almost reaches the full swing. In order to meet the easy-to-carry application, the modulator chip uses a low power design idea, so that the whole system has the lowest power consumption. Through this design, the circuit design flow from system modeling, circuit design, layout design to chip design has been formed. In this paper, a fully differential switched capacitor (DSC) structure is adopted. The Sigma-Delta modulator is realized by using the 0.5 渭 m L50w CMOS process of MXIC. The power supply voltage is 5 V. The simulation results show that the signal bandwidth is 7.8 KHz and the sampling frequency is 1MHz. The input amplitude of the modulator is 卤4V, the maximum signal-to-noise ratio is 111.3 dB, the effective bit number is about 18 bits and the power consumption is about 6.6 MW. The Sigma-Delta modulator is suitable for A / D converters with high precision, power consumption and input swing.
【学位授予单位】：苏州大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN761
本文编号：2208565
[Abstract]:Due to the rapid development of SOC chips in recent years, high precision and low power ADC chips have attracted more and more attention. In this context, the purpose of this paper is to achieve high precision, low power consumption, wide input swing A / D converter. Sigma-Delta modulator is an effective way to realize high resolution A / D converter under the current LSI technology. The A / D converter using Sigma-Delta modulator can achieve 16 bits or more resolution. This structure is not easily affected by the non-ideal factors of analog circuits. Under the current technological conditions, it is relatively easy to achieve low-cost, high-performance analog-to-digital converters. However, it is difficult for Sigma-Delta ADC to convert high speed signal, and the difficulty of analog circuit increases the design difficulty of decimation filter. In this paper, the Sigma-Delta modulator is mainly studied in the aspects of high precision, low power consumption and wide input swing. The high order Sigma-Delta modulator needs to consider the stability problem. In order to ensure the stability of the system, the 2-2MASH structure is adopted in the Sigma-Delta modulator. In order to reduce 1 / f noise and offset noise, chopper stabilization technique is used in the integrator of the first stage of the modulator. The feedforward factor, feedback factor and integrator gain factor are obtained by MATLAB software modeling and system simulation. By using a new set of design coefficients, the overload input level of the modulator almost reaches the full swing. In order to meet the easy-to-carry application, the modulator chip uses a low power design idea, so that the whole system has the lowest power consumption. Through this design, the circuit design flow from system modeling, circuit design, layout design to chip design has been formed. In this paper, a fully differential switched capacitor (DSC) structure is adopted. The Sigma-Delta modulator is realized by using the 0.5 渭 m L50w CMOS process of MXIC. The power supply voltage is 5 V. The simulation results show that the signal bandwidth is 7.8 KHz and the sampling frequency is 1MHz. The input amplitude of the modulator is 卤4V, the maximum signal-to-noise ratio is 111.3 dB, the effective bit number is about 18 bits and the power consumption is about 6.6 MW. The Sigma-Delta modulator is suitable for A / D converters with high precision, power consumption and input swing.
【学位授予单位】：苏州大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN761
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，本文编号：2208565
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