基于Verilog-AMS的信号监测比较器模块行为模型设计

发布时间：2018-08-29 11:06

【摘要】：随着SoC复杂度和集成度不断提升,数模混合信号系统的应用变得更加普及和多样化。在混合系统设计验证过程中,如果在各个阶段都采用Spice模型仿真验证的方法,会大幅延长验证的周期和减缓设计迭代的速度,而全部采用数字离散功能模型,又丢失模拟部分的仿真精度和性能参数。论文结合已经成熟的混合信号建模方法,对信号监测比较器进行分析和建模,达到仿真速度和精度的折衷,从而满足混合信号系统验证要求和需要。本文基于Verilog-AMS平台主要分析和建立了有信号监测功能的比较器电路完整的行为模型。论文首先介绍了该电路的应用背景和Verilog-AMS平台的特点,然后介绍数模转换器和比较器的工作原理和主要结构,通过这些介绍和对比分析得出论文建模对象所用的电路结构。最后系统的将信号监测比较器电路分解为结构和功能相互独立的各个电路模块,通过理论分析各模块功能的行为特点,建立相应的行为模型,使用Verilog-AMS语言对行为模型进行描述,同时采用Cadence模混合仿真软件对各行为模型进行仿真,并对电路模型和真实电路仿真结果进行了对比和分析。通过仿真结果可知比较器模型的开环增益为80dB,相比于Spice仿真其误差为1.25%,；低速和高速模式下建立时间分别为38.8μs和2.2μs,相比与Spice仿真误差均在15%内；DAC部分在3V和1.5V参考基准源下建立时间分别为79ns和63ns,工作电流为9.1μA,相比于Spice仿真建立时间误差均在15%以内,电流误差在3.3%；系统总的工作电流为21μA,相比于Spice仿真误差为10%。对比Spice仿真结果表明通过这种方法对数模混合信号电路建立行为级模型能够不仅能够在一定程度上反映电路的真实的物理特性和保证仿真精度,在速度上还有不低于50倍的提升,从而加快设计和验证进程。
[Abstract]:With the increasing complexity and integration of SoC, the applications of digital-analog mixed signal systems become more and more popular and diversified. In the process of hybrid system design verification, if the method of Spice model simulation is used in every stage, the period of verification will be greatly prolonged and the speed of design iteration will be slowed down, and the digital discrete function model will be adopted. The simulation accuracy and performance parameters are also lost. Combined with the mature modeling method of mixed signal, the paper analyzes and models the signal monitor comparator, and achieves the tradeoff between the speed and precision of simulation, so as to meet the requirements and requirements of the mixed signal system verification. Based on Verilog-AMS platform, a complete circuit behavior model of comparator with signal monitoring function is analyzed and established in this paper. This paper first introduces the application background of the circuit and the characteristics of the Verilog-AMS platform, then introduces the working principle and main structure of the digital-to-analog converter and comparator. Through these introductions and comparative analysis, the circuit structure used in the paper modeling object is obtained. Finally, the circuit of the signal monitoring comparator is decomposed into each circuit module with independent structure and function. Through the theoretical analysis of the behavior characteristics of each module function, the corresponding behavior model is established, and the behavior model is described by Verilog-AMS language. At the same time, each behavior model is simulated by Cadence modular hybrid simulation software, and the circuit model and the real circuit simulation results are compared and analyzed. The simulation results show that the open-loop gain of the comparator model is 80 dB, and the error of the comparator model is 1.25 compared with the Spice simulation, the time of setting up at low speed and high speed mode is 38.8 渭 s and 2.2 渭 s, respectively, and the error is less than 15% compared with that of Spice simulation. The establishment time of the DAC part is 79ns and 63ns under the reference source of 3V and 1.5V, the operating current is 9.1 渭 A, compared with the Spice simulation, the time error is less than 15%, and the current error is 3.30.The total operating current of the system is 21 渭 A, and the error is 10% compared with the Spice simulation error. Compared with the Spice simulation results, it is shown that this method can not only reflect the real physical characteristics of the circuit, but also guarantee the simulation accuracy. There is also a speed increase of not less than 50 times, thus speeding up the design and validation process.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47

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