半导体器件与集成电路的ESD防护技术研究与实现
发布时间：2018-09-03 16:38
【摘要】：随着半导体技术的不断发展,人们对器件可靠性方面的研究也越来越深入,静电放电对器件的危害得到了更多的重视。随着对器件抗静电能力要求的提高,一些符合原来标准要求的器件也需要提升其抗静电能力。在此背景下,对以下内容进行了分析和研究:1、对现有的一款JFET器件结构和实现流程进行了分析,并在TCAD软件环境下编写器件的仿真程序,建立了器件结构及杂质分布;2、对器件进行了基本参数仿真,在对比仿真结果与实际参数差别的基础上,通过TCAD软件仿真对现有器件的ESD能力进行了评估与分析,仿真结果表明:器件的ESD能力大于4KV;3、对ESD失效的器件样品进行了分析,分别提出了器件接触孔版图的优化设计,增加镇流电阻使ESD电流分布更加均匀;对器件金属层版图设计规则进行调整,增大器件的源、漏金属间距,提高器件两极间的ESD电压的承受能力;对器件的场氧化层工艺进行调整,增加源、漏两极压焊点下的介质层厚度,使器件在经过粘接压焊工艺后的抗ESD击穿能力得到提高。最后实现了器件的ESD能力达到4KV以上;4、对器件的ESD测试方法进行了对比分析,针对器件成品ESD测试在时间以及成本上的不足,提出了一种在硅片上对器件进行ESD能力进行评估的简易的晶圆级测试方法,并证明了这种测试方法在器件的研制阶段可对各方案的ESD能力进行有效的评估。
[Abstract]:With the development of semiconductor technology, more and more research on the reliability of devices has been carried out, and the harm of electrostatic discharge to devices has been paid more attention. With the improvement of the antistatic ability of the devices, some devices that meet the requirements of the original standard also need to improve their antistatic ability. Under this background, the following contents are analyzed and studied: 1, the structure and implementation flow of an existing JFET device are analyzed, and the simulation program of the device is written under the environment of TCAD software. The device structure and impurity distribution are established, and the basic parameters of the device are simulated. On the basis of comparing the simulation results with the actual parameters, the ESD capability of the existing devices is evaluated and analyzed by TCAD software simulation. The simulation results show that the ESD capability of the device is more than 4KV ~ (3). The sample of ESD is analyzed, and the optimum design of the contact hole layout is put forward, and the distribution of ESD current is more uniform by increasing the ballast resistance. Adjust the layout rules of the metal layer of the device, increase the distance between the source and drain metal of the device, improve the withstand capacity of the ESD voltage between the two poles of the device, adjust the field oxidation layer process of the device, increase the source, The thickness of the dielectric layer under the pressure solder joint of the leakage two poles improves the ESD breakdown resistance of the device after the bonding process. Finally, the ESD capability of the device is up to more than 4% of 4KV. The ESD testing method of the device is compared and analyzed, aiming at the shortage of time and cost of the ESD test of the finished device. A simple wafer level test method is proposed to evaluate the ESD capability of the devices on silicon wafer. It is proved that this method can effectively evaluate the ESD capability of each scheme in the development stage of the device.
【学位授予单位】：北京工业大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN305;O441.1;TN40
本文编号：2220555
[Abstract]:With the development of semiconductor technology, more and more research on the reliability of devices has been carried out, and the harm of electrostatic discharge to devices has been paid more attention. With the improvement of the antistatic ability of the devices, some devices that meet the requirements of the original standard also need to improve their antistatic ability. Under this background, the following contents are analyzed and studied: 1, the structure and implementation flow of an existing JFET device are analyzed, and the simulation program of the device is written under the environment of TCAD software. The device structure and impurity distribution are established, and the basic parameters of the device are simulated. On the basis of comparing the simulation results with the actual parameters, the ESD capability of the existing devices is evaluated and analyzed by TCAD software simulation. The simulation results show that the ESD capability of the device is more than 4KV ~ (3). The sample of ESD is analyzed, and the optimum design of the contact hole layout is put forward, and the distribution of ESD current is more uniform by increasing the ballast resistance. Adjust the layout rules of the metal layer of the device, increase the distance between the source and drain metal of the device, improve the withstand capacity of the ESD voltage between the two poles of the device, adjust the field oxidation layer process of the device, increase the source, The thickness of the dielectric layer under the pressure solder joint of the leakage two poles improves the ESD breakdown resistance of the device after the bonding process. Finally, the ESD capability of the device is up to more than 4% of 4KV. The ESD testing method of the device is compared and analyzed, aiming at the shortage of time and cost of the ESD test of the finished device. A simple wafer level test method is proposed to evaluate the ESD capability of the devices on silicon wafer. It is proved that this method can effectively evaluate the ESD capability of each scheme in the development stage of the device.
【学位授予单位】：北京工业大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN305;O441.1;TN40
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