新型无结场效应晶体管的研究

发布时间：2018-09-19 05:51

【摘要】：随着半导体技术的不断发展,作为大型集成电路基本单元的金属氧化物半导体场效应晶体管的尺寸在逐渐地按比例缩小,换句话说就是MOSFET中的半导体结的距离越来越短,现在已经达到几十纳米甚至几纳米。器件尺寸缩小的主要目的是为了增加集成电路的集成度,但是这样会使器件工艺制造过程面临巨大的挑战,同时也会给器件性能带来一些难以避免的负面影响。由于原子扩散和自然统计分布,在几十纳米甚至几纳米的距离内制造出半导体结是相当困难的,它需要进行的热预算以及超高的退火技术几乎难以实现;沟道长度缩小会带来严重的短沟道效应,会对器件性能造成严重的影响。为了解决纳米级尺寸下MOSFET遇到的一系列难以克服的难题,许多科研团队开始研究无结场效应晶体管并提出了许多新型结构的无结半导体器件。论文就是对新型无结场效应晶体管的研究,其中包括I形栅无结场效应晶体管和U沟道无结场效应晶体管。论文所提出的I形栅以及U沟道无结场效应晶体管的最基本模型是简单无结场效应晶体管,其导通原理相当于一个栅控电阻。因为无结场效应晶体管的沟道与源漏区均是同种物质且均匀掺杂,所以它的体内不存在任何金属结,这不仅可以避免器件在制造工艺上遇到的难题,而且可以有效的抑制短沟道效应;I形栅无结场效应晶体管是对普通无结场效应晶体管栅极形状进行的一种优化结果,与普通无结场效应晶体管相比,具有更加优越的电学性能。而U沟道无结场效应晶体管是继对一般平面无结场效应晶体管的大量研究之后所推出的新型结构。U沟道无结场效应晶体管与普通无结晶体管相比,在结构上多出了两个垂直于水平沟道的部分,这样设计结构的优点在于,在芯片面积不变的情况下,器件的有效沟道的长度会变大,从而在深纳米级尺寸下可以进一步减小器件对短沟道效应的敏感程度;通过调节垂直部分的高度还可以有效的减小GIDL以及GISL电流。论文使用SILVACO TCAD半导体仿真软件对新型结构的无结场效应晶体管进行仿真模拟,并通过改变器件各项参数来确定各个参数变化对晶体管性能造成的不同影响,分析数据并结合器件基本原理以解释仿真得到的基本电学特性结果,从而最大化得到对应尺寸下的性能最优的I形栅或U沟道无结场效应晶体管,为以后同类晶体管的应用发展做出有利的基础准备。
[Abstract]:With the continuous development of semiconductor technology, the size of metal oxide semiconductor field effect transistors, which are the basic units of large integrated circuits, is gradually shrinking proportionally. In other words, the distance between semiconductor junctions in MOSFET is getting shorter and shorter. It has now reached tens of nanometers or even a few nanometers. The main purpose of device size reduction is to increase the integration of integrated circuits, but this will make the process of device manufacturing face great challenges, but also will bring some unavoidable negative effects on the device performance. Due to atomic diffusion and natural statistical distribution, it is very difficult to fabricate semiconductor junctions in tens of nanometers or even several nanometers, and it is difficult to achieve the thermal budget and ultra-high annealing technology. The shortening of channel length will bring about serious short channel effect and will seriously affect the performance of the device. In order to solve a series of difficult problems encountered by MOSFET in nanoscale size, many researchers have begun to study the junction free field effect transistors (FET) and have proposed a number of novel structures of uncoupled semiconductor devices. In this paper, we study the novel junction free field effect transistors, including I gate non junction field effect transistors and U channel non junction field effect transistors. The most basic model of I-gate and U-channel non-junction field-effect transistor proposed in this paper is simple no-junction field-effect transistor, whose principle of conduction is equivalent to that of a gate controlled resistor. Because the channels and drain areas of the junction free field effect transistors are homogenous and uniformly doped, there are no metal junctions in the transistors, which can not only avoid the difficulties encountered in the fabrication process of the devices. Moreover, it can effectively suppress the short channel effect / I gate field effect transistor. It is an optimization result of the gate shape of the common non junction field effect transistor. Compared with the common non junction field effect transistor, it has better electrical performance. The U-channel non-junction field-effect transistor is a new structure developed after a lot of research on the general planar non-junction field effect transistor. The U-channel non-junction field effect transistor is compared with the ordinary non-junction transistor. Two more parts perpendicular to the horizontal channel are added to the structure, so the advantage of the design is that the effective channel length of the device becomes larger when the chip area is constant. Thus the sensitivity of the device to the short channel effect can be further reduced under the deep nanoscale size, and the GIDL and GISL currents can be effectively reduced by adjusting the height of the vertical part. In this paper, the SILVACO TCAD semiconductor simulation software is used to simulate the novel junction free field effect transistor, and by changing the device parameters to determine the different effects of each parameter on the performance of the transistor. By analyzing the data and combining the basic principle of the device to explain the basic electrical characteristics obtained by simulation, we can maximize the performance of I-gate or U-channel field-effect transistor without junction under the corresponding size. For the future development of similar transistors to make a favorable foundation for the development.
【学位授予单位】：沈阳工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN386

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