用于UHF RFID阅读器芯片的完全前馈式多比特Delta-Sigma调制器设计

发布时间：2018-10-07 20:33

【摘要】：不同于Nyquist模数转换器,Delta-Sigma模数转换器由于其不需要精确的无源器件匹配,在越来越多的领域扮演重要的角色。本文基于0.18μm CMOS工艺,根据UHF RFID阅读器芯片的要求设计了一款用于模数转换的开关电容型Delta-Sigma调制器,取得的工作成果如下：1、在基本理论方面,首先根据线性模型详细分析了Delta-Sigma调制器的基本工作原理并且分析了其三种常见结构的特点。此外根据非线性的模型分析了Delta-Sigma调制器的稳定性。最后分析了其对于采样时钟的要求。2、系统设计上,采用了单环三阶四比特量化结构,其环路滤波器采用完全前馈结构实现。通过行为级仿真验证了其相对于传统反馈结构的优势：各级积分器的输出摆幅小于参考电压的10%,这将大大减轻对于运放性能的要求。此外,通过DWA技术抑制了非理想多比特反馈DAC的问题。最后,通过行为级仿真来确定了各个模块电路的性能指标。3、电路设计上,采用一种闭环的有源求和电路,使系统能够处理更大的输入信号幅度(-1dBFS)。由于其闭环结构,相对开环的求和电路,其对工艺的偏差不敏感。此外还对该电路的非理想特性进行了定性分析从而指导求和电路中运放结构的选取。4、完成了调制器模拟电路部分所有的晶体管级电路设计与版图设计。后仿真结果表明,调制器在48MHz采样速度下能够在1.5MHz带宽内达到12比特以上的有效位数,在3.3V电源电压下消耗电流5mA。本论文受国家自然科学基金《超高频射频识别读写器芯片的多噪声建模与优化方法研究》(61306034)和《移动式UHF RFID阅读器防碰撞问题研究与测试验证》(61302005)资助。
[Abstract]:Unlike Nyquist analog-to-digital converters, Delta-Sigma analog-to-digital converters play an important role in more and more fields because they do not require accurate passive device matching. Based on 0.18 渭 m CMOS technology and according to the requirements of UHF RFID reader chip, a switched capacitor Delta-Sigma modulator for A / D conversion is designed in this paper. The results are as follows: 1. Firstly, the basic principle of Delta-Sigma modulator is analyzed in detail according to the linear model and the characteristics of its three common structures are analyzed. In addition, the stability of Delta-Sigma modulator is analyzed according to the nonlinear model. Finally, the requirement of sampling clock is analyzed. In the system design, the single-loop three-order four-bit quantization structure is adopted, and the loop filter is realized with the complete feedforward structure. The behavior-level simulation verifies its advantage over the traditional feedback structure: the output swing of the integrator is smaller than that of the reference voltage, which will greatly reduce the performance requirements of the operational amplifier. In addition, the problem of non-ideal multi-bit feedback DAC is restrained by DWA technology. Finally, the performance index of each module circuit is determined by behavior-level simulation. In the circuit design, a closed-loop active summation circuit is used to make the system process larger input signal amplitude (-1dBFS). Because of its closed loop structure, it is insensitive to process deviation relative to the open-loop summation circuit. In addition, the non-ideal characteristics of the circuit are qualitatively analyzed to guide the selection of the operational amplifier structure in the summation circuit. Finally, all the transistor level circuit design and layout design of the modulator analog circuit are completed. The simulation results show that the modulator can achieve more than 12 bits in the 1.5MHz bandwidth at 48MHz sampling speed, and consume a current of 5 Ma at 3.3 V supply voltage. This thesis is supported by the National Natural Science Foundation of China, "Research on Multi-noise Modeling and Optimization of UHF RFID Reader Chip" (61306034) and "Research and Test Verification of Anti-collision of Mobile UHF RFID Reader" (61302005).
【学位授予单位】：华东师范大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TP391.44;TN761

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