基带处理器芯片的低功耗设计实现
发布时间：2018-10-13 10:35
【摘要】：现今集成电路的发展也伴随着移动互联网的发展以及手持设备的广泛运用,集成电路的功耗变成除时钟频率以及面积外又一个值得关注的问题。而低功耗技术则变成了集成电路设计中值得研究的课题。本文分析了CMOS电路功耗的主要组成,其组成主要分为静态功耗以及动态功耗。并且按照芯片设计的不同阶段研究了目前常用的低功耗设计方法,主要设计阶段包括系统设计、电路设计、电路综合以及设计实现过程中。数字电路的低功耗设计是贯穿于芯片设计的整个阶段。目前常用的低功耗设计方法有门控时钟、多阈值电压、电源关掉、多电源供电技术等。同时本文以武汉芯泰公司基带处理芯片BB为研究对象,后端设计采用的工艺为SMIC130nm G,主要在电路综合以及版图设计阶段实现低功耗设计。并针对该芯片,本文按照设计阶段的不同,首先在电路综合阶段研究了结点电容优化、多阈值电压技术、操作数隔离技术、门控时钟技术对电路动态功耗以及静态功耗优化的程度。同时在版图设计阶段着重研究了使用UPF/CPF电源约束对基带处理芯片BB进行电源关掉设计以及时钟树综合低功耗实现。经过多方面的实验,结点电容技术对功耗的优化能达到2%、多阈值电压设计对功耗的优化能达到28%、操作数隔离技术在多组合电路中的功耗优化能达到15%、门控时钟技术在多时序电路中优化能达到70%、低功耗时钟树技术对时钟树的功耗优化能达到50%
[Abstract]:With the development of mobile Internet and the wide use of handheld devices, the power consumption of integrated circuits has become a problem worth paying attention to besides clock frequency and area. Low-power technology has become a subject worth studying in integrated circuit design. In this paper, the main components of CMOS circuit power consumption are analyzed, including static power consumption and dynamic power consumption. And according to the different stages of chip design, the commonly used low-power design methods are studied. The main design stages include system design, circuit synthesis and the process of design and implementation. The low power design of digital circuit runs through the whole stage of chip design. The commonly used low-power design methods include gated clock, multi-threshold voltage, power off, multi-power supply technology and so on. At the same time, this paper takes the baseband processing chip BB of Wuhan Xintai Company as the research object. The back-end design process is SMIC130nm G, which mainly realizes the low-power design in the stage of circuit synthesis and layout design. According to the different design stages, this paper first studies the node capacitance optimization, multi-threshold voltage technology, Operand isolation technology in the circuit synthesis stage. The degree to which the gated clock technology optimizes the dynamic and static power consumption of the circuit. At the same time, in the layout design phase, the power off design of baseband processing chip BB using UPF/CPF power constraints and the implementation of clock tree synthesis with low power consumption are studied. After many experiments, Node capacitance technology can optimize power consumption by 2 steps, multi-threshold voltage design can optimize power consumption by 28 steps, Operand isolation technology can achieve 15 steps in multi-combinational circuits, and gated clock technology can be used to optimize power consumption in multi-sequential circuits. The conversion energy can reach 70%, and the low power clock tree technology can optimize the power consumption of the clock tree by 50%.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402
[Abstract]:With the development of mobile Internet and the wide use of handheld devices, the power consumption of integrated circuits has become a problem worth paying attention to besides clock frequency and area. Low-power technology has become a subject worth studying in integrated circuit design. In this paper, the main components of CMOS circuit power consumption are analyzed, including static power consumption and dynamic power consumption. And according to the different stages of chip design, the commonly used low-power design methods are studied. The main design stages include system design, circuit synthesis and the process of design and implementation. The low power design of digital circuit runs through the whole stage of chip design. The commonly used low-power design methods include gated clock, multi-threshold voltage, power off, multi-power supply technology and so on. At the same time, this paper takes the baseband processing chip BB of Wuhan Xintai Company as the research object. The back-end design process is SMIC130nm G, which mainly realizes the low-power design in the stage of circuit synthesis and layout design. According to the different design stages, this paper first studies the node capacitance optimization, multi-threshold voltage technology, Operand isolation technology in the circuit synthesis stage. The degree to which the gated clock technology optimizes the dynamic and static power consumption of the circuit. At the same time, in the layout design phase, the power off design of baseband processing chip BB using UPF/CPF power constraints and the implementation of clock tree synthesis with low power consumption are studied. After many experiments, Node capacitance technology can optimize power consumption by 2 steps, multi-threshold voltage design can optimize power consumption by 28 steps, Operand isolation technology can achieve 15 steps in multi-combinational circuits, and gated clock technology can be used to optimize power consumption in multi-sequential circuits. The conversion energy can reach 70%, and the low power clock tree technology can optimize the power consumption of the clock tree by 50%.
【学位授予单位】：华中科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402
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