一种带参考注入信号的TIADC时间失配校准算法
发布时间：2018-10-15 19:31
【摘要】：提出了一种带参考注入信号的校准算法,用于校准时间交织模数转换器(Time-Interleaved Analog-to-Digital Converter,TIADC)的时间失配误差。该算法引入参考注入信号,参考注入信号通过采样保持电路(sample hold circuit,S/H)后,利用TIADC的各子通道时钟依次控制S/H,对其输出后的值进行运算获得时间误差,再将时间误差反馈回多相时钟产生器,利用可变延迟线实现时间失配的补偿。该算法运算简单,消耗的硬件资源低,对输入信号没有限制,可以扩展到任意通道。算法应用于一个4通道12 bits的TIADC,当输入信号的归一化频率f_(in)/f_s=0.485 0,设定的最大误差为1.0% T_s时,MATLAB仿真结果表明,经过本算法校准后的SFDR从31.009 4 dB提高到了95.627 0 dB,SNDR从31.074 9 dB提高到了73.480 5 dB,证明了该校准方案的有效性。
[Abstract]:A calibration algorithm with reference injection signal is proposed to calibrate the time mismatch of time Interleaved Analog-to-Digital Converter (Time-Interleaved Analog-to-Digital Converter,TIADC). The reference injection signal is introduced in the algorithm. After the reference injection signal is sampled and held by (sample hold circuit,S/H), the clock of each sub-channel of TIADC is used to control S / H in turn, and the time error is obtained by calculating the output value. Then the time error is fed back to the polyphase clock generator and the time mismatch is compensated by the variable delay line. The algorithm is simple in operation, low in hardware resources and unlimited in input signal, and can be extended to any channel. The algorithm is applied to a 4-channel 12 bits TIADC, when the input frequency f _ (in) / f_s=0.485 0 is normalized, and the maximum error is 1.0% T _ s. The simulation results of MATLAB show that, The effectiveness of the proposed calibration scheme is proved by the improved SFDR from 31.009 4 dB to 95.627 0 dB,SNDR from 31.074 9 dB to 73.480 5 dB,.
【作者单位】： 合肥工业大学微电子设计研究所;
【分类号】：TN792
本文编号：2273604
[Abstract]:A calibration algorithm with reference injection signal is proposed to calibrate the time mismatch of time Interleaved Analog-to-Digital Converter (Time-Interleaved Analog-to-Digital Converter,TIADC). The reference injection signal is introduced in the algorithm. After the reference injection signal is sampled and held by (sample hold circuit,S/H), the clock of each sub-channel of TIADC is used to control S / H in turn, and the time error is obtained by calculating the output value. Then the time error is fed back to the polyphase clock generator and the time mismatch is compensated by the variable delay line. The algorithm is simple in operation, low in hardware resources and unlimited in input signal, and can be extended to any channel. The algorithm is applied to a 4-channel 12 bits TIADC, when the input frequency f _ (in) / f_s=0.485 0 is normalized, and the maximum error is 1.0% T _ s. The simulation results of MATLAB show that, The effectiveness of the proposed calibration scheme is proved by the improved SFDR from 31.009 4 dB to 95.627 0 dB,SNDR from 31.074 9 dB to 73.480 5 dB,.
【作者单位】： 合肥工业大学微电子设计研究所;
【分类号】：TN792
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