12位250MSPS流水线ADC关键设计技术研究
发布时间：2018-10-17 09:21
【摘要】：现代集成电路中,模数转换器(ADC)是将现实世界的模拟信号转换为数字信号系统可以处理的形式的基础模块。随着CMOS工艺的持续缩减,增长的器件截止频率与更小的寄生电容使得数字电路可以实现更节能、更快速地逻辑电路,也使得在一个芯片上实现更复杂、更大的系统成为了可能。然而,同样随工艺发展而改变的器件参数,例如更低的本征输出电阻,更低的供电电压,更大的漏电流以及更加多变的器件特性,成为模拟电路设计最大的挑战。简而言之,越是先进的工艺,器件的本征增益也就越低。因此,高性能的转换器的设计也面临全新的挑战。在各种不同类型的ADC中,流水线ADC是一种可以很好地折衷速度、精度、面积和功耗等重要性能参数的模数转换器。因此被广泛地应用于高速的无线通信电子系统中。本文首先对流水线ADC的系统结构、电路原理进行了分析与研究。冗余校准算法是流水线ADC电路结构的基础,使采用若干低量化位数的流水线级来构成高量化位数的ADC成为可能。然后,对运放的开关电容电路是如何实现MDAC电路中S/H电路、Sub-DAC、减法器、放大器等模块的功能进行原理介绍与实例分析。其次分析了MDAC电路的位数与电路的各性能参数之间的关系,并综合考虑后,做出电路结构的最优选择。针对本文选用的SHA-less结构中所存在的时钟偏差问题也进行了简要的分析与讨论,给出了时钟偏差的校准思路与方法。基于TSMC 65nm CMOS技术,本文设计实现了一款分辨率为12 bit、采样速率为250MS/s的流水线ADC。分析了电路设计过程中参数的计算,功能的实现,主要是对流水线ADC中的关键电路MDAC的实现,并对其工作过程进行了详细地公式推导。第一级MDAC中所采用的运放也进行了详细地原理分析,以及性能提升技术的学习,选定了最终的结构并进行了认真的计算推导、仿真验证,调整再仿真,最终达到了相当水平的性能。第四章中就第三章中所设计的电路进行了系统的仿真,给出了运放模块、第一级MDAC模块以及整体流水线ADC电路的仿真验证,结果表明,达到了设计的目的。电路的电源电压为2.5V,输入电压范围-1~+1V,时钟频率为250MS/s。仿真结果表明,输入的差分正弦信号频率为10.7MHz时,第一级输出有效位数达到14.87 bit,无杂散动态范围(SFDR)为98.6 dB,信噪失真比(SNDR)为91.3 dB。同时,整体ADC的ENOB为11.96 bit,SFDR和SNDR分别为86.7 dB和73.7 dB。当输入信号频率为108MHz时,第一级MDAC的ENOB为13.89 bit,SFDR和SNDR分别为90.3 dB和85.38 dB,整体电路有效位数为11.81 bit,SFDR和SNDR分别为81.9dB和72.86 dB。仿真结果表明,本设计能满足设计的目标。同时在中频(IF)采样时,依然有足够的电路特性。
[Abstract]:In modern integrated circuits, the analog-to-digital converter (ADC) is a basic module that converts real world analog signals into digital signal systems. As the CMOS process continues to shrink, increasing device cutoff frequencies and smaller parasitic capacitors make it possible for digital circuits to achieve more energy efficient, faster logic circuits and more complex, larger systems on a single chip. However, the device parameters, such as lower intrinsic output resistance, lower supply voltage, larger leakage current and more variable device characteristics, are the biggest challenges in analog circuit design. In short, the more advanced the process, the lower the intrinsic gain of the device. Therefore, the design of high-performance converters also faces new challenges. Among different types of ADC, pipelined ADC is an analog-to-digital converter that can compromise the important performance parameters such as speed, precision, area and power consumption. Therefore, it is widely used in high-speed wireless communication electronic systems. Firstly, the system structure and circuit principle of pipelined ADC are analyzed and studied in this paper. Redundant calibration algorithm is the basis of pipelined ADC circuit structure, which makes it possible to use pipeline of low quantization bits to construct ADC with high quantization bit. Then, how to realize the function of S / H circuit, Sub-DAC, subtractor, amplifier and so on in MDAC circuit is introduced and an example is given. Secondly, the relationship between the bit number of MDAC circuit and the performance parameters of the circuit is analyzed, and the optimal selection of the circuit structure is made after comprehensive consideration. This paper also briefly analyzes and discusses the clock deviation problem in the SHA-less structure selected in this paper, and gives the calibration thought and method of the clock deviation. Based on TSMC 65nm CMOS technology, a pipelined ADC. with a resolution of 12 bit, sampling rate of 250MS/s is designed and implemented in this paper. In this paper, the calculation of parameters and the realization of function in circuit design are analyzed. The key circuit MDAC in pipelined ADC is mainly realized, and its working process is deduced in detail. The operational amplifier used in the first stage MDAC is also analyzed in detail, and the learning of the performance improvement technology is also carried out. Finally, the final structure is selected, and the calculation, deduction, simulation verification, adjustment and resimulation are carried out. Finally, the performance is quite high. In the fourth chapter, the circuit designed in chapter 3 is simulated systematically, and the simulation verification of the operational amplifier module, the first stage MDAC module and the whole pipeline ADC circuit is given. The result shows that the purpose of the design is achieved. The supply voltage of the circuit is 2.5 V, the input voltage range is -1 ~ 1 V, and the clock frequency is 250 Ms / s. The simulation results show that when the input frequency of the differential sinusoidal signal is 10.7MHz, the effective bit number of the first stage output reaches 14.87 bit, (SFDR) is 98.6 dB, the signal-noise-to-noise ratio (SNDR) is 91.3 dB.. Meanwhile, the ENOB of the whole ADC is 11.96 bit,SFDR and the SNDR is 86.7 dB and 73.7 dB., respectively. When the input signal frequency is 108MHz, the ENOB of the first stage MDAC is 13.89 bit,SFDR and the SNDR is 90.3 dB and 85.38 dB,. The effective bits of the whole circuit are 11.81 bit,SFDR and 72.86 dB., respectively. Simulation results show that the design can meet the design objectives. At the same time, if (IF) sampling, there are still enough circuit characteristics.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
[Abstract]:In modern integrated circuits, the analog-to-digital converter (ADC) is a basic module that converts real world analog signals into digital signal systems. As the CMOS process continues to shrink, increasing device cutoff frequencies and smaller parasitic capacitors make it possible for digital circuits to achieve more energy efficient, faster logic circuits and more complex, larger systems on a single chip. However, the device parameters, such as lower intrinsic output resistance, lower supply voltage, larger leakage current and more variable device characteristics, are the biggest challenges in analog circuit design. In short, the more advanced the process, the lower the intrinsic gain of the device. Therefore, the design of high-performance converters also faces new challenges. Among different types of ADC, pipelined ADC is an analog-to-digital converter that can compromise the important performance parameters such as speed, precision, area and power consumption. Therefore, it is widely used in high-speed wireless communication electronic systems. Firstly, the system structure and circuit principle of pipelined ADC are analyzed and studied in this paper. Redundant calibration algorithm is the basis of pipelined ADC circuit structure, which makes it possible to use pipeline of low quantization bits to construct ADC with high quantization bit. Then, how to realize the function of S / H circuit, Sub-DAC, subtractor, amplifier and so on in MDAC circuit is introduced and an example is given. Secondly, the relationship between the bit number of MDAC circuit and the performance parameters of the circuit is analyzed, and the optimal selection of the circuit structure is made after comprehensive consideration. This paper also briefly analyzes and discusses the clock deviation problem in the SHA-less structure selected in this paper, and gives the calibration thought and method of the clock deviation. Based on TSMC 65nm CMOS technology, a pipelined ADC. with a resolution of 12 bit, sampling rate of 250MS/s is designed and implemented in this paper. In this paper, the calculation of parameters and the realization of function in circuit design are analyzed. The key circuit MDAC in pipelined ADC is mainly realized, and its working process is deduced in detail. The operational amplifier used in the first stage MDAC is also analyzed in detail, and the learning of the performance improvement technology is also carried out. Finally, the final structure is selected, and the calculation, deduction, simulation verification, adjustment and resimulation are carried out. Finally, the performance is quite high. In the fourth chapter, the circuit designed in chapter 3 is simulated systematically, and the simulation verification of the operational amplifier module, the first stage MDAC module and the whole pipeline ADC circuit is given. The result shows that the purpose of the design is achieved. The supply voltage of the circuit is 2.5 V, the input voltage range is -1 ~ 1 V, and the clock frequency is 250 Ms / s. The simulation results show that when the input frequency of the differential sinusoidal signal is 10.7MHz, the effective bit number of the first stage output reaches 14.87 bit, (SFDR) is 98.6 dB, the signal-noise-to-noise ratio (SNDR) is 91.3 dB.. Meanwhile, the ENOB of the whole ADC is 11.96 bit,SFDR and the SNDR is 86.7 dB and 73.7 dB., respectively. When the input signal frequency is 108MHz, the ENOB of the first stage MDAC is 13.89 bit,SFDR and the SNDR is 90.3 dB and 85.38 dB,. The effective bits of the whole circuit are 11.81 bit,SFDR and 72.86 dB., respectively. Simulation results show that the design can meet the design objectives. At the same time, if (IF) sampling, there are still enough circuit characteristics.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792
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